Add header to handle Octeon fuse access.
Signed-off-by: NAaron Williams <awilliams@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This header includes the Octeon feature detection used in many Octeon
drivers.
Signed-off-by: NAaron Williams <awilliams@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This header includes common register defines and accessor functions.
Signed-off-by: NAaron Williams <awilliams@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This patch adds the necessary lowlevel init code, to enable SMP Linux
booting. This code will be used with the platform specific Octeon Linux
boot command "bootoctlinux", which starts a configurable number of cores
into Linux.

Additionally some erratas and lowlevel register initializations are
copied from the original Cavium / Marvell U-Boot source code, enabling
booting into the Linux kernel.
Signed-off-by: NStefan Roese <sr@denx.de>

Add the #ifdef __ASSEMBLY__ checks to enable inclusion of this header
from assembler files.
Signed-off-by: NStefan Roese <sr@denx.de>

This patch enables USB support with some helpful commands, like fs
support.
Signed-off-by: NStefan Roese <sr@denx.de>

Add the USB device tree nodes to the Octeon dts/dtsi files.
Signed-off-by: NStefan Roese <sr@denx.de>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

As noticed while working on the USB xHCI support, Octeon needs to flush
all pending writes so that the values are present in the memory. Add
this "syncw" instruction (twice) to flush_dcache_range().
Signed-off-by: NStefan Roese <sr@denx.de>

Import platform specific mangle-port.h header, allowing a area specific
swapping, which is needed on Octeon for USB & PCI areas.

Imported from Linux v5.7.
Signed-off-by: NStefan Roese <sr@denx.de>

Import octeon_should_swizzle_table[] which is needed for the area
specific swapping. It will be used by the platform specific
mangle-port.h header.

Imported from Linux v5.7.
Signed-off-by: NStefan Roese <sr@denx.de>

This patch adds the glue layer for the MIPS Octeon SoCs. It's ported
mainly from the Linux code.
Signed-off-by: NStefan Roese <sr@denx.de>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>

Octeon uses mapped addresses for virtual and physical memory. It's not
that easy to calculate the resulting addresses here. So let's remove
this BUG_ON() completely, as it's not really helpful.

Please also note, that BUG_ON() is not recommended any more in the Linux
kernel.
Signed-off-by: NStefan Roese <sr@denx.de>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>

On MIPS platforms, mapping of the base address is needed. This patch
switches from dev_get_addr() to dev_remap_addr() to get the mapped base
address of the xHCI controller.
Signed-off-by: NStefan Roese <sr@denx.de>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>

This patch adds the board specific configuration (struct) for the
Octeon 3 EBB7304 EVK. This struct is ported from the 2013er Cavium /
Marvell U-Boot repository. Also, the Octeon RAM driver is enabled in
the board defconfig for its usage.

Tested with one and two DIMMs on the EBB7304 EVK (8 & 16 GiB).
Signed-off-by: NStefan Roese <sr@denx.de>

This patch adds the initialization call for the Octeon RAM driver to
the Octeon platforms code. So if enabled via Kconfig, the DDR driver
will be called and the RAM will be configured and used. If the RAM
driver is not enabled, the L2 cache is still used as RAM.
Signed-off-by: NStefan Roese <sr@denx.de>

This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot
repository. It currently supports DDR4 on Octeon 3. It can be later
extended to support also DDR3 and Octeon 2 platforms.

Part 3 includes the DIMM SPD handling code and the Kconfig / Makefile
integration.
Signed-off-by: NAaron Williams <awilliams@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot
repository. It currently supports DDR4 on Octeon 3. It can be later
extended to support also DDR3 and Octeon 2 platforms.

Part 2 includes the very complex Octeon 3 DDR4 configuration
Signed-off-by: NAaron Williams <awilliams@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot
repository. It currently supports DDR4 on Octeon 3. It can be later
extended to support also DDR3 and Octeon 2 platforms.

Part 1 adds the base U-Boot RAM driver, which will be instantiated by
the DT based probing.
Signed-off-by: NAaron Williams <awilliams@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This header will be used by the DDR driver (lmc). Its ported from the
2013 Cavium / Marvell U-Boot repository.
Signed-off-by: NAaron Williams <awilliams@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This header will be used by the DDR driver (lmc). Its ported from the
2013 Cavium / Marvell U-Boot repository.
Signed-off-by: NAaron Williams <awilliams@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This header is used by the upcoming DDR driver and potentially by other
drivers ported from the 2013 Cavium / Marvell U-Boot repository.
Signed-off-by: NAaron Williams <awilliams@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This patch adds the memory controller (LMC) DT node to the Octeon 3 dtsi
file. It also adds the L2C DT node, as this is referenced by the DDR
driver.
Signed-off-by: NStefan Roese <sr@denx.de>

Pull request for UEFI sub-system for efi-2021-01-rc1

The following bugs in the UEFI system are resolved:

* illegal free in EFI_LOAD_FILE2_PROTOCOL implementation
* incorrect documentation of EFI_LOAD_FILE2_PROTOCOL implementation
* output of CRC32 as decimal instead hexadecimal in unit test
* use EfiReservedMemoryType for no-map reserved memory
* avoid unnecessary resets in UEFI unit tests
* call EFI bootmgr even without having /EFI/boot

- generate unique mac address from SoC serial on S400 board
- Add USB support for GXL and AXG SoCs
- Update Gadget code to use the new GXL and AXG USB glue driver
- Add a VIM3 board support to add dynamic PCIe enable in OS DT
- Fix AXG pinmux with requesting GPIOs
- Add missing GPIOA_18 for AXG pinctrl
- Add Amlogic PWM driver

The device tree may contain a /reserved-memory node. The no-map property
of the sub-nodes signals if the memory may be accessed by the UEFI payload
or not.

In the EBBR specification (https://github.com/arm-software/ebbr) the
modeling of the reserved memory has been clarified.

If a reserved memory node in the device tree has the no-map property map,
create a EfiReservedMemoryType memory map entry else use
EfiBootServicesData.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

CONFIG_EFI_GRUB_ARM32 is only needed for architectures with caches that are
not managed via CP15 (or for some outdated buggy versions of GRUB). It
makes more sense to disable the setting per architecture than per defconfig.

Move QEMU's CONFIG_EFI_GRUB_ARM32_WORKAROUND=n from defconfig to Kconfig.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

There is an extra space.
Signed-off-by: NSean Anderson <seanga2@gmail.com>
Reviewed-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

Currently, the EFI bootmgr is only called if there is a EFI binary
inside the path for removable media is found, i.e. /EFI/boot/. This
doesn't make sense. It is the duty of the bootmgr to find out the
path and name of the EFI binary to boot. It should be called even
if there is no /EFI/boot directory.

Thus, call the bootmgr before we try to boot the EFI binary inside
the removable media path.

Also remove the ${fdtcontroladdr} parameter because the fallback is
handled in cmd/bootefi.c and that already takes care of correct settings
if the board has ACPI and thus no device tree at all.
Signed-off-by: NMichael Walle <michael@walle.cc>
Reviewed-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

When we do not execute a test requiring ExitBootServices do not reset the
system after testing.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

Print the CRC32 loaded via the EFI_LOAD_FILE2_PROTOCOL as a hexadecimal
number.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: NIlias Apalodimas <ilias.apalodimas@linaro.org>

Add code to use %x in efi_st_print().
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

strsep() changes the address that its first argument points to.
We cannot use the changed address as argument of free().
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: NIlias Apalodimas <ilias.apalodimas@linaro.org>

U-Boot offers a EFI_LOAD_FILE2_PROTOCOL which the Linux EFI stub can use to
load an initial RAM disk. Update the function comments of the
implementation.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: NIlias Apalodimas <ilias.apalodimas@linaro.org>

Rsync all defconfig files using moveconfig.py
Signed-off-by: NTom Rini <trini@konsulko.com>

Bring in the assorted changes that have been staged in the 'next' branch
prior to release.
Signed-off-by: NTom Rini <trini@konsulko.com>

This adds the driver for the PWM controller found in the Amlogic SoCs.

This PWM is only a set of Gates, Dividers and Counters:
PWM output is achieved by calculating a clock that permits calculating
two periods (low and high). The counter then has to be set to switch after
N cycles for the first half period.
The hardware has no "polarity" setting. This driver reverses the period
cycles (the low length is inverted with the high length) for
PWM_POLARITY_INVERSED.

Disabling the PWM stops the output immediately (without waiting for the
current period to complete first).
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>

Add the missing GPIOA_18 from the missing EE gpio list.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>

The AXG pmx driver gpio request offset needs the pin base to have the
correct pin number.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Reviewed-by: NMark Kettenis <kettenis@openbsd.org>

The VIM3 on-board  MCU can mux the PCIe/USB3.0 shared differential
lines using a FUSB340TMX USB 3.1 SuperSpeed Data Switch between
an USB3.0 Type A connector and a M.2 Key M slot.
The PHY driving these differential lines is shared between
the USB3.0 controller and the PCIe Controller, thus only
a single controller can use it.

This adds this dynamic switching right before booting Linux
and the configuration steps in the boards documentation.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Reviewed-by: NKevin Hilman <khilman@baylibre.com>
Tested-by: NKevin Hilman <khilman@baylibre.com>
[narmstrong: fixed warning by replacing min() by min_t()]

Use the newly added VIM3 board support instead of the generic W400.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Reviewed-by: NKevin Hilman <khilman@baylibre.com>
Tested-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>