- 17 9月, 2016 27 次提交
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由 Simon Glass 提交于
Move this option to Kconfig and tidy up existing uses. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Move this option to Kconfig and tidy up existing uses. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Move this option to Kconfig and tidy up existing uses. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
This converts the following to Kconfig: CONFIG_SPL_NET_VCI_STRING Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Move this option to Kconfig and tidy up existing uses. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Move this option to Kconfig and tidy up existing uses. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Move this option to Kconfig and tidy up existing uses. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Move this option to Kconfig and tidy up existing uses. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Move this option to Kconfig and tidy up existing uses. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Move this option to Kconfig and tidy up existing uses. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Move this option to Kconfig and tidy up existing uses. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Move this option to Kconfig and tidy up existing uses. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Move this option to Kconfig and tidy up existing uses. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Move this option to Kconfig and tidy up existing uses. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Move this option to Kconfig and tidy up existing uses. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Move this option to Kconfig and tidy up existing uses. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Move this option to Kconfig and tidy up existing uses. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Move this option to Kconfig and tidy up existing uses. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Move this option to Kconfig and tidy up existing uses. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Move this option to Kconfig and tidy up existing uses. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Move this option to Kconfig and tidy up existing uses. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Move this option to Kconfig and tidy up existing uses. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
There are a few options which use lower case. We should use upper case for all CONFIG options. Signed-off-by: NSimon Glass <sjg@chromium.org> [trini: Add usbtty/nand hunk to include/configs/spear3xx_evb.h] Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Simon Glass 提交于
A few boards define this in a header file which is incorrect. It means that Kconfig options that rely on this cannot be used. Move it. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
A few boards define this in a header file which is incorrect. It means that Kconfig options that rely on this cannot be used. Move it. Note that quite a few boards defined this options but do not appear to actually use SPL: BSC9132QDS_NOR_DDRCLK100_SECURE BSC9132QDS_NOR_DDRCLK133_SECURE BSC9132QDS_SDCARD_DDRCLK100_SECURE BSC9132QDS_SDCARD_DDRCLK133_SECURE BSC9132QDS_SPIFLASH_DDRCLK100_SECURE BSC9132QDS_SPIFLASH_DDRCLK133_SECURE C29XPCIE_NOR_SECBOOT P1010RDB-PA_36BIT_NAND_SECBOOT P1010RDB-PA_36BIT_SPIFLASH_SECBOOT P1010RDB-PA_NAND_SECBOOT P1010RDB-PA_NOR_SECBOOT P1010RDB-PB_36BIT_NOR_SECBOOT P1010RDB-PB_36BIT_SPIFLASH_SECBOOT P1010RDB-PB_NAND_SECBOOT P1010RDB-PB_NOR_SECBOOT P3041DS_SECURE_BOOT P4080DS_SECURE_BOOT P5020DS_NAND_SECURE_BOOT P5040DS_SECURE_BOOT T1023RDB_SECURE_BOOT T1024QDS_DDR4_SECURE_BOOT T1024QDS_SECURE_BOOT T1024RDB_SECURE_BOOT T1040RDB_SECURE_BOOT T1042D4RDB_SECURE_BOOT T1042RDB_SECURE_BOOT T2080QDS_SECURE_BOOT T2080RDB_SECURE_BOOT T4160QDS_SECURE_BOOT T4240QDS_SECURE_BOOT ls1021aqds_nor_SECURE_BOOT ls1021atwr_nor_SECURE_BOOT ls1043ardb_SECURE_BOOT For these boards CONFIG_SPL_DM will no-longer be defined in SPL. But since they apparently don't have an SPL, this should not matter. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Move the SPL settings into common/spl where most of the SPL code is kept. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Update the defconfig files to match their canonical form, as produced by 'make safedefconfig'. This is the result of running 'tools/moveconfig.py -s' on the tree. Signed-off-by: NSimon Glass <sjg@chromium.org>
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- 10 9月, 2016 2 次提交
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由 Heiko Schocher 提交于
move VERSION_VARIABLE from board config file into a Kconfig option. Signed-off-by: NHeiko Schocher <hs@denx.de>
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由 Tom Rini 提交于
In some cases we were missing CONFIG_USB=y so enable that when needed. Reviewed-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NTom Rini <trini@konsulko.com>
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- 09 9月, 2016 1 次提交
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由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@konsulko.com>
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- 07 9月, 2016 10 次提交
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由 Masahiro Yamada 提交于
If both SPL_DM and SPL_OF_CONTROL are enabled, SPL needs to bind several devices, but CONFIG_SYS_MALLOC_F_LEN=0x400 is apparently not enough. Increase the default to 0x2000 for the case. This will be helpful for shorter defconfigs. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: NStefan Roese <sr@denx.de> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Madan Srinivas 提交于
An issue in the TI secure image generation tool causes the ROM to load the SPL at a different load address than what is specified by CONFIG_ISW_ENTRY_ADDR while doing a peripheral boot on HS devices. This causes the SPL to fail on secure devices during peripheral boot. The TI secure image generation tool has been fixed so that the SPL will always be loaded at 0x403018E0 by the ROM code for both peripheral and memory boot modes. Signed-off-by: NMadan Srinivas <madans@ti.com> Reviewed-by: NNishanth Menon <nm@ti.com> Acked-by: NLokesh Vutla <lokeshvutla@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Andreas Dannenberg 提交于
Enable the platform-specific post-processing of FIT-extracted blobs such as Kernel, DTB, and initramfs on TI AM57xx high-security (HS) devices which will ultimately invoke a ROM-based API call that performs secure processing such as blob authentication. Signed-off-by: NAndreas Dannenberg <dannenberg@ti.com> Signed-off-by: NAndrew F. Davis <afd@ti.com> Reviewed-by: NLokesh Vutla <lokeshvutla@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Andreas Dannenberg 提交于
Enable the platform-specific post-processing of FIT-extracted blobs such as Kernel, DTB, and initramfs on TI DRA7xx high-security (HS) devices which will ultimately invoke a ROM-based API call that performs secure processing such as blob authentication. Signed-off-by: NAndreas Dannenberg <dannenberg@ti.com> Signed-off-by: NAndrew F. Davis <afd@ti.com> Reviewed-by: NLokesh Vutla <lokeshvutla@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Andreas Dannenberg 提交于
Enable the platform-specific post-processing of FIT-extracted blobs such as Kernel, DTB, and initramfs on TI AM43xx high-security (HS) devices which will ultimately invoke a ROM-based API call that performs secure processing such as blob authentication. Signed-off-by: NAndreas Dannenberg <dannenberg@ti.com> Signed-off-by: NAndrew F. Davis <afd@ti.com> Reviewed-by: NLokesh Vutla <lokeshvutla@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Beniamino Galvani 提交于
Remove the device definition from board file, update the driver with the new compatible property and update config with necessary options. Signed-off-by: NBeniamino Galvani <b.galvani@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Alexander Graf 提交于
On the raspberry pi, you can disable the serial port to gain dynamic frequency scaling which can get handy at times. However, in such a configuration the serial controller gets its rx queue filled up with zero bytes which then happily get transmitted on to whoever calls getc() today. This patch adds detection logic for that case by checking whether the RX pin is mapped to GPIO15 and disables the mini uart if it is not mapped properly. That way we can leave the driver enabled in the tree and can determine during runtime whether serial is usable or not, having a single binary that allows for uart and non-uart operation. Signed-off-by: NAlexander Graf <agraf@suse.de> Acked-by: NStephen Warren <swarren@wwwdotorg.org> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Fabio Estevam 提交于
NXP kernel expects to boot in secure mode, so introduce warp7_secure_defconfig target which selects CONFIG_ARMV7_BOOT_SEC_DEFAULT. Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
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由 Fabio Estevam 提交于
Since commit a13d3757 ("warp: Use imx_ddr_size() for calculating the DDR size") warp board no longer boots. The reason for the breakage is that the warp board is using the DDR configuration from mx6slevk. A fundamental difference between warp and mx6slevk is that warp only uses one DDR chip select while mx6slevk uses two. The imx_ddr() function calculates the RAM size in runtime by reading the values of registers MDCTL and MDMISC. So in order to fix this warp boot issue, create a imximage DDR file specific to warp, where the MDCTL register is configured to only activates a single chip select. Reported-by: NBreno Lima <breno.lima@nxp.com> Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com> Tested-by: NBreno Lima <breno.lima@nxp.com>
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由 Akshay Bhat 提交于
Add support for Advantech DMS-BA16 board. The board is based on Advantech BA16 module which has a i.MX6D processor. The board supports: - FEC Ethernet - USB Ports - SDHC and MMC boot - SPI NOR - LVDS and HDMI display Basic information about the module: - Module manufacturer: Advantech - CPU: Freescale ARM Cortex-A9 i.MX6D - SPECS: Up to 2GB Onboard DDR3 Memory; Up to 16GB Onboard eMMC NAND Flash Supports OpenGL ES 2.0 and OpenVG 1.1 HDMI, 24-bit LVDS 1x UART, 2x I2C, 8x GPIO, 4x Host USB 2.0 port, 1x USB OTG port, 1x micro SD (SDHC),1x SDIO, 1x SATA II, 1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2 Signed-off-by: NAkshay Bhat <akshay.bhat@timesys.com> Cc: u-boot@lists.denx.de Cc: sbabic@denx.de
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