Incorporate DMA driver from legacy LPCLinux NXP BSP.
The files taken from the legacy patch are:
- lpc32xx DMA driver
- lpc3250 header file DMA registers definition.

The legacy driver was updated and clean-up as part of the integration with the latest u-boot.
Signed-off-by: NSylvain Lemieux <slemieux@tycoint.com>
Acked-by: NMarek Vasut <marex@denx.de>
Tested-by: NVladimir Zapolskiy <vz@mleia.com>

The change adds support of LPC32xx SLC NAND controller.

LPC32xx SoC has two different mutually exclusive NAND controllers to
communicate with single and multiple layer chips.

This simple driver allows to specify NAND chip timings and defines
custom read_buf()/write_buf() operations, because access to 8-bit data
register must be 32-bit aligned.

Support of hardware ECC calculation is not implemented (data
correction is always done by software), since it requires a working
DMA engine.

The driver can be included to an SPL image.
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>
Acked-by: NScott Wood <scottwood@freescale.com>
Tested-by: NSylvain Lemieux <slemieux@tycoint.com>

LPC32xx MAC and clock control configuration requires some minor quirks
to deal with a phy connected by RMII.

It's worth to mention that the kernel and legacy BSP from NXP sets
SUPP_RESET_RMII == (1 << 11) bit, however the description of this bit is
missing in shared LPC32x0 User Manual UM10326 Rev. 3, July 22, 2011
and in LPC32x0 Draft User Mannual Rev. 00.27, November 20, 2008, also
in my tests an SMSC LAN8700 phy device connected over RMII seems to
work correctly without touching this bit.

Add support of RMII, if CONFIG_RMII is defined, this option is aligned
with a number of boards, which already define the same config value.
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>
Tested-by: NSylvain Lemieux <slemieux@tycoint.com>

Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Signed-off-by: NAlbert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>

This driver only supports Driver Model, not legacy model.
Signed-off-by: NAlbert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>

Signed-off-by: NAlbert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>

The controller's Reed-Solomon ECC hardware is
used except of course for raw reads and writes.
It covers in- and out-of-band data together.

The SPL framework is supported.
Signed-off-by: NAlbert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>

Signed-off-by: NAlbert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>

Signed-off-by: NWolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: NTom Rini <trini@ti.com>

This change adds initial support for NXP LPC32x0 SoC series.
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: NMarek Vasut <marek.vasut@gmail.com>