Update PLL values.
SYS_CLKSEL value for 20MHz is changed to 2. In other platforms
SYS_CLKSEL value 2 represents reserved. But in sys_clk array
ind 1 is used for 13Mhz. Since other platforms are not using
13Mhz, reusing index 1 for 20MHz.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NSricharan R <r.sricharan@ti.com>

Updating pinmux data as specified in the latest DM
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NBalaji T K <balajitk@ti.com>

Update pbias programming sequence for OMAP5 ES2.0/DRA7
Signed-off-by: NBalaji T K <balajitk@ti.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

NON SECURE SRAM is 512KB in DRA7xx devices.
So fixing it here.
Signed-off-by: NSricharan R <r.sricharan@ti.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

The sys_clk on the dra evm board is 20MHZ.
Changing the configuration for the same.
And also moving V_SCLK, V_OSCK defines to
arch/clock.h for OMAP4+ boards.
Signed-off-by: NSricharan R <r.sricharan@ti.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

Serial UART is connected to UART1. So add the change
for the same.
Signed-off-by: NSricharan R <r.sricharan@ti.com>

Slew rate compensation cells are not present for DRA7xx
Soc's. So return from function srcomp_enable() if soc is not
OMAP54xx.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

DRA752 now uses AVS Class 0 voltages which are voltages in efuse.

This means that we can now use the optimized voltages which are
stored as mV values in efuse and program PMIC accordingly.

This allows us to go with higher OPP as needed in the system without
the need for implementing complex AVS logic.
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

In DRA7xx Soc's voltage scaling is done using GPI2C.
So i2c_init should happen before scaling. I2C driver
uses __udelay which needs timer to be initialized.
So moving timer_init just before voltage scaling.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

TPS659038 is the power IC used in DRA7XX boards.
Adding support for this and also adding pmic data
for DRA7XX boards.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

The registers that are used for device identification
are changed from OMAP5 to DRA7xx.
Using the correct registers for DRA7xx.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

Voltage scaling can be done in two ways:
-> Using SR I2C
-> Using GP I2C
In order to support both, have a function pointer in pmic_data
so that we can call as per our requirement.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

To be consistent with other ARM platforms,
renaming asm/arch-omap*/clocks.h to asm/arch-omap*/clock.h
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

SGX clocks should be enabled only for OMAP5 ES1.0.
So this can be removed.
Signed-off-by: NSricharan R <r.sricharan@ti.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

After having the u-boot clean up series, there are
many definitions that are unused in header files.
Removing all those unused ones.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

The newly introduced function setup_warmreset_time(), called
from within prcm_init(), tries to write to the prm_rsttime
OMAP5 register. The struct member holding this register's
address is however initialized for OMAP5 ES2.0 only. On ES1.0
devices this uninitialized value causes a second (warm) reset
at startup.

Add .prm_rsttime address init to the ES1.0 struct.
Signed-off-by: NLubomir Popov <lpopov@mm-sol.com>
Acked-by: NTom Rini <trini@ti.com>

Patch adds a call of abb_setup() function, and proper registers
definitions needed for ABB setup sequence. ABB is initialized
for MPU voltage domain.
Signed-off-by: NAndrii Tseglytskyi <andrii.tseglytskyi@ti.com>

Adaptive Body Biasing (ABB) modulates transistor bias voltages
dynamically in order to optimize switching speed versus leakage.
Adaptive Body-Bias ldos are present for some voltage domains
starting with OMAP3630. There are three modes of operation:

* Bypass - the default, it just follows the vdd voltage
* Foward Body-Bias - applies voltage bias to increase transistor
  performance at the cost of power.  Used to operate safely at high
  OPPs.
* Reverse Body-Bias - applies voltage bias to decrease leakage and
  save power.  Used to save power at lower OPPs.
Signed-off-by: NAndrii Tseglytskyi <andrii.tseglytskyi@ti.com>
Acked-by: NNishanth Menon <nm@ti.com>

Not doing so breaks cases where CPSW is not required such as for USB RNDIS network boot.
Signed-off-by: NJoel A Fernandes <joelagnel@ti.com>

Conflicts:
	drivers/serial/Makefile

The non-SPL build of U-Boot on Tegra only runs on a single CPU, and
hence there is no need to enable the SCU when running U-Boot. If an
SMP OS is booted, and it needs the SCU enabled, it will enable the SCU
itself. U-Boot doing so is redundant.

The one exception is Tegra20, where an enabled SCU is required for some
aspects of PCIe to work correctly.

Some Tegra SoCs contain CPUs without a software-controlled SCU. In this
case, attempting to turn it on actively causes problems. This is the case
for Tegra114. For example, when running Linux, the first (or at least
some very early) user-space process will trigger the following kernel
message:

Unhandled fault: imprecise external abort (0x406) at 0x00000000

This is typically accompanied by that process receving a fatal signal,
and exiting. Since this process is usually pid 1, this causes total
system boot failure.
Signed-off-by: NTom Warren <twarren@nvidia.com>
[swarren, fleshed out description, ported to upstream chipid APIs]
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

No need to use the 'status' variable, so just remove it.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: NOtavio Salvador <otavio@ossystems.com.br>

When running the "save" command several times on a mx6qsabresd we see:

U-Boot > save
Saving Environment to MMC...
Writing to MMC(1)... done
U-Boot > save
Saving Environment to MMC...
MMC partition switch failed
U-Boot > save
Saving Environment to MMC...
Writing to MMC(1)... done
U-Boot > save
Saving Environment to MMC...
MMC partition switch failed
U-Boot > save
Saving Environment to MMC...
Writing to MMC(1)... done
U-Boot > save
Saving Environment to MMC...
MMC partition switch failed

This issue is caused by the incorrect usage of CONFIG_SYS_MMC_ENV_PART.

CONFIG_SYS_MMC_ENV_PART should be used to specify the mmc partition that stores
the environment variables.

On some imx boards it is been incorrectly used to pass the partition of kernel
and dtb files for the 'mmcpart' script variable.

Remove the CONFIG_SYS_MMC_ENV_PART usage and configure the 'mmcpart' variable
directly.
Reported-by: NJason Liu <r64343@freescale.com>
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Acked-by: NJason Liu <r64343@freescale.com>

We need to call the save_omap_boot_params function on am33xx/ti81xx and
other newer TI SoCs, so move the function to boot-common.  Only OMAP4+
has the omap_hw_init_context function so add ifdefs to not call it on
am33xx/ti81xx.  Call save_omap_boot_params from s_init on am33xx/ti81xx
boards.
Reviewed-by: NR Sricharan <r.sricharan@ti.com>
Signed-off-by: NTom Rini <trini@ti.com>

Prior to Sricharan's cleanup of the boot parameter saving code, we
did not make use of NON_SECURE_SRAM_START on am33xx, so it wasn't a
problem that the address was pointing to the middle of our running SPL.
Correct to point to the base location of the download image area.
Increase CONFIG_SPL_TEXT_BASE to account for this scratch area being
used.  As part of correcting these tests, make use of the fact that
we've always been placing our stack outside of the download image area
(which is fine, once the downloaded image is run, ROM is gone) so
correct the max size test to be the ROM defined top of the download area
to where we link/load at.
Signed-off-by: NTom Rini <trini@ti.com>

---
Changes in v2:
- Fix typo noted by Peter Korsgaard

Only called in this file, mark as static.
Signed-off-by: NTom Rini <trini@ti.com>

Add minimal support (only boot from mmc device) for the Congatec
Conga-QEVAl Evaluation Carrier Board with conga-Qmx6q (i.MX6 Quad
processor) module.
Signed-off-by: NLeo Sartre <lsartre@adeneo-embedded.com>
Acked-by: NStefano Babic <sbabic@denx.de>
Acked-by: NOtavio Salvador <otavio@ossystems.com.br>

Signed-off-by: NOtavio Salvador <otavio@ossystems.com.br>

Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

The boot logo matching is now done in following way:

 - use LOGO_BMP if it is set, or
 - use $(BOARD).bmp if it exists in tools/logos, or
 - use $(VENDOR).bmp if it exists in tools/logos, or
 - use denx.bmp otherwise.
Signed-off-by: NOtavio Salvador <otavio@ossystems.com.br>
Acked-by: NWolfgang Denk <wd@denx.de>

The number of gpio signal is packed inside CONFIG_SF_DEFAULT_CS macro
(shifted and or'ed with chip select), so it's incorrect to pass
that macro directly as an argument to gpio_direction_output() call.

Also, SPI driver sets the direction and initial value of a gpio,
used as a chip select signal, before any actual activity happens
on the bus.

So, it is safe to just remove the gpio_direction_output call,
that works incorrectly, thus making no effect, anyway.
Signed-off-by: NAndrew Gabbasov <andrew_gabbasov@mentor.com>
Tested-by: NRobert Winkler <robert.winkler@boundarydevices.com>
Acked-by: NDirk Behme <dirk.behme@de.bosch.com>

There are 3 IO expanders on the mx6qsabreauto all reset by the
same GPIO, just set it to high to use the IO.
Signed-off-by: NRenato Frias <b13784@freescale.com>
Acked-by: NStefano Babic <sbabic@denx.de>

Add i2c2 and 3 to mx6qsabreauto board, i2c3 is multiplexed
use gpio to set steering.
Signed-off-by: NRenato Frias <b13784@freescale.com>
Reviewed-by: NOtavio Salvador <otavio@ossystems.com.br>
Reviewed-by: NFabio Estevam <fabio.estevam@freescale.com>
Acked-by: NStefano Babic <sbabic@denx.de>

When the mx6slevk board support was added in U-boot there was no device tree
support for mx6sl, so only a FSL 3.0.35 was tested at that time.

Now that mx6slevk support is available we can boot a device tree kernel, by
adjusting CONFIG_LOADADDR into a proper location, so that a non-dt and a dt
kernels can be booted.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

The vectoring table has to be placed at 0x0, but U-Boot on MX23/MX28
starts from RAM, so the vectoring table at 0x0 is not present. Craft
code that will be placed at 0x0 and will redirect interrupt vectoring
to proper location of the U-Boot in RAM.
Signed-off-by: NMarek Vasut <marex@denx.de>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: NFabio Estevam <fabio.estevam@freescale.com>

VF610TWR is a board based on Vybrid VF610 SoC.

This patch adds basic support for Vybrid VF610TWR board.
Signed-off-by: NAlison Wang <b18965@freescale.com>
Signed-off-by: NJason Jin <Jason.jin@freescale.com>
Signed-off-by: NTsiChung Liew <tsicliew@gmail.com>
Reviewed-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

This patch adds Vybrid VF610 to mxc_ocotp document.
Signed-off-by: NAlison Wang <b18965@freescale.com>
Reviewed-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

This patch adds lpuart support for Vybrid VF610 platform.
Signed-off-by: NTsiChung Liew <tsicliew@gmail.com>
Signed-off-by: NAlison Wang <b18965@freescale.com>

This patch adds watchdog support for Vybrid VF610 platform.
Signed-off-by: NAlison Wang <b18965@freescale.com>

This patch adds FEC support for Vybrid VF610 platform.

In function fec_open(), RCR register is only set as RGMII mode. But RCR
register should be set as RMII mode for VF610 platform.
This configuration is already done in fec_reg_setup(), so this piece of
code could just leave untouched the FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII /
FEC_RCNTRL_MII_MODE bits.
Signed-off-by: NAlison Wang <b18965@freescale.com>
Reviewed-by: NBenoit Thebaudeau <benoit.thebaudeau@advansee.com>
Reviewed-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>