- 30 3月, 2018 21 次提交
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由 Wilson Ding 提交于
This patch enabled PCIe port on both devel-board and espressobin board. Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NWilson Ding <dingwei@marvell.com> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Wilson Ding 提交于
Signed-off-by: NWilson Ding <dingwei@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Wilson Ding 提交于
This patch introduced the Aardvark PCIe driver based driver model. The PCIe driver is supposed to work in Root Complex mode. It only supports X1 lane width. Signed-off-by: NWilson Ding <dingwei@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38725Reviewed-by: NVictor Gu <xigu@marvell.com> Reviewed-by: NHua Jing <jinghua@marvell.com> Tested-by: NHua Jing <jinghua@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Wilson Ding 提交于
This patch added a new region of 32MiB AT 0xe800.0000 to Armada37x0's memory map. This region is supposed to be mapped in MMU in order to enable the access to the PCI I/O or MEM resources. Signed-off-by: NWilson Ding <dingwei@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38724Tested-by: NiSoC Platform CI <ykjenk@marvell.com> Reviewed-by: NVictor Gu <xigu@marvell.com> Signed-off-by: NKen Ma <make@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ken Ma 提交于
Since the new pinctrl/gpio driver is used, so this patch removes the old board specific pin control settings. Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ken Ma 提交于
The commit "arm64: mvebu: Add pinctrl nodes for Armada 3700" has added new pinctrl nodes. This reverts commit f7cab0f9. Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ken Ma 提交于
Reviewed-on: http://vgitil04.il.marvell.com:8080/43289Tested-by: NiSoC Platform CI <ykjenk@marvell.com> Reviewed-by: NKostya Porotchkin <kostap@marvell.com> Reviewed-by: NIgal Liberman <igall@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ken Ma 提交于
This patch corrects below mpp definitions for armada 3720 DB board and ESPRESSOBin board: - "smi" pins group is added and "smi" function is set for eth0; - Now pcie pins are used as gpio to implement PCIe function in hardware, so "pcie" group function is changed to "gpio". Reviewed-on: http://vgitil04.il.marvell.com:8080/43287Reviewed-by: NHua Jing <jinghua@marvell.com> Tested-by: NiSoC Platform CI <ykjenk@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ken Ma 提交于
This patch corrects below mpp definitions: - The sdio_sb group is composed of 6 pins and not 5; - The rgmii group contains pins mpp2[17:6] and not mpp2[19:6]; - Pin of group "pmic0" is mpp1[6] but not mpp1[16]; - Pin of group "pmic1" is mpp1[7] but not mpp1[17]; - A new group "smi" is added in A0 with 2 pins - mpp2[19:18], its bitmask is bit4; - Group "pcie1" has 3 pins in A0 - mpp2[5:3], its bit mask is bit5 | bit9 | bit10 but not bit4; - Group "ptp" has 3 pins in A0 as Z1, but its bitmask is changed to bit11 | bit12 | bit13. Reviewed-on: http://vgitil04.il.marvell.com:8080/43288Tested-by: NiSoC Platform CI <ykjenk@marvell.com> Reviewed-by: NHua Jing <jinghua@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ken Ma 提交于
For armada_37xx_update_reg(), the parameter offset should be pointer so that it can be updated, otherwise offset will keep old value, and then when offset is larger than or equal to 32 the mask calculated by "BIT(offset)" will be 0 in gpio chip hook functions, it's an error, this patch set offset parameter of armada_37xx_update_reg() as pointer. Reviewed-on: http://vgitil04.il.marvell.com:8080/43287Reviewed-by: NHua Jing <jinghua@marvell.com> Tested-by: NiSoC Platform CI <ykjenk@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ken Ma 提交于
Pin 23 on South bridge does not belong to the rgmii group. It belongs to a separate group which can have 3 functions. Due to this the fix also have to update the way the functions are managed. Until now each groups used NB_FUNCS(which was 2) functions. For the mpp23, 3 functions are available but it is the only group which needs it, so on the loop involving NB_FUNCS an extra test was added to handle only the functions added. The bug was visible when the gpio regulator used the gpio 23, the whole rgmii group was setup to gpio which broke the Ethernet support on the Armada 3720 DB board. Thanks to this patch, the UHS SD cards (which need the vqmmc) _and_ the Ethernet work again. Reviewed-on: http://vgitil04.il.marvell.com:8080/43284Reviewed-by: NHua Jing <jinghua@marvell.com> Tested-by: NiSoC Platform CI <ykjenk@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ken Ma 提交于
The number of pins in South Bridge is 30 and not 29. There is a fix for the driver for the pinctrl, but a fix is also need at device tree level for the GPIO. Reviewed-on: http://vgitil04.il.marvell.com:8080/43286Reviewed-by: NHua Jing <jinghua@marvell.com> Tested-by: NiSoC Platform CI <ykjenk@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ken Ma 提交于
On the south bridge we have pin from 0 to 29, so it gives 30 pins (and not 29). Reviewed-on: http://vgitil04.il.marvell.com:8080/43285Tested-by: NiSoC Platform CI <ykjenk@marvell.com> Reviewed-by: NHua Jing <jinghua@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ken Ma 提交于
Add mmc pins, pcie pins and sdio pins definition and do these pins' configuration for DB board and espressobin board; Add uart2 pins configuration for DB board. Reviewed-on: http://vgitil04.il.marvell.com:8080/40914Reviewed-by: NWilson Ding <dingwei@marvell.com> Tested-by: NWilson Ding <dingwei@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ken Ma 提交于
Reviewed-on: http://vgitil04.il.marvell.com:8080/40913Reviewed-by: NWilson Ding <dingwei@marvell.com> Tested-by: NWilson Ding <dingwei@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ken Ma 提交于
This patch enable the PINCTRL and GPIO support, including the GPIO command on the Armada 3720 espressobin board. Reviewed-on: http://vgitil04.il.marvell.com:8080/40746Tested-by: NiSoC Platform CI <ykjenk@marvell.com> Reviewed-by: NWilson Ding <dingwei@marvell.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ken Ma 提交于
Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NKen Ma <make@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Mark Kettenis 提交于
The various load address values are taken from the a37xx configuration and match the dowstream 'u-boot-2017.03-armada-17.10' release where appropriate. Signed-off-by: NMark Kettenis <kettenis@openbsd.org> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Alexander Graf 提交于
The kwbimage format is reading beyond its header structure if it misdetects a Xilinx Zynq image and tries to read it. Fix it by sanity checking that the header we want to read fits inside our file size. Signed-off-by: NAlexander Graf <agraf@suse.de> Tested-by: NMichal Simek <michal.simek@xilinx.com> Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Baruch Siach 提交于
This makes the network devices usable when booting a blank board over UART, with no pre-configured MAC address stored in the environment area. Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Igal Liberman 提交于
Currently, ATU (address translation unit) implementation doesn't support translate addresses > 32 bits. This patch allows to configure ATU correctly for different memory accesses (memory, configuration and IO). The same approach is used in Linux Kernel. Signed-off-by: NIgal Liberman <igall@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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- 26 3月, 2018 4 次提交
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git://git.denx.de/u-boot-microblaze由 Tom Rini 提交于
Xilinx changes for v2018.05 - Fix mkimage recognition - Update all my fragments ZynqMP: - Use clk driver - Support loading elfs in el1 - Various DTS and defconfig changes - Enable newer pmufw versions - Support more clocks - Remove ep108 - Secure image support - Fix memtest setup Zynq: - Enabling watchdog driver - Support more clocks - defconfig changes fpga: - Simplify error path net: - GMII case update
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- 24 3月, 2018 4 次提交
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由 Petr Vorel 提交于
Signed-off-by: NPetr Vorel <petr.vorel@gmail.com>
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由 Petr Vorel 提交于
Introduce another difference from upstream (kernel) source in fs/ubifs/super.c: adding preprocessor condition as y variable in mount_ubifs() depends on CONFIG_UBIFS_SILENCE_MSG: fs/ubifs/super.c:1337:15: error: variable ?y? set but not used [-Werror=unused-but-set-variable] long long x, y; Not setting CONFIG_UBIFS_SILENCE_MSG in am335x_igep003x_defconfig and igep0032_defconfig. Although it was defined in their config headers, it depends on CMD_UBIFS which is not set for them. Signed-off-by: NPetr Vorel <petr.vorel@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Heiko Schocher <hs@denx.de>
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由 Petr Vorel 提交于
Use of CONFIG_UBIFS_SILENCE_MSG was added in 147162da ("ubi: ubifs: Turn off verbose prints") Then it was removed in ff94bc40 ("mtd, ubi, ubifs: resync with Linux-3.14") Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Heiko Schocher <hs@denx.de> Signed-off-by: NPetr Vorel <petr.vorel@gmail.com>
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由 Sjoerd Simons 提交于
The ti,pindir-d0-out-d1-in property is not expected to have a value according to the device-tree binding, so treat it as a boolean not a uint property. Signed-off-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: NJagan Teki <jagan@openedev.com>
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- 23 3月, 2018 11 次提交
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git://git.denx.de/u-boot-arc由 Tom Rini 提交于
Alexey: 1. Significantly rework cache-related functionality. In particular that fixes coherency problems in some corner-cases, allows us to enable and disable caches in run-time and still have properly running system, finally support execution from real flash (before we used to run from DDR from the very beginning). 2. Remove string routines implemented in assembly. That allows us to build and run U-Boot on wide range of ARC cores with different configurations. I.e. whatever tuning is used on GCC's command-line we'll get code for desired flavor of ARC. Otherwise for each and every corner-case we would need to add ifdefs in assembly code to accommodate missing instructions etc. 3. Get use of GCC's garbage collector which helps to slim-down resulting image quite a bit. 4. Also now we may disable U-Boot self-relocation for ARC if needed either by platform or for debugging purposes.
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由 Eugeniy Paltsev 提交于
Refactor GO and PREP subcommands implementation for a simpler override in the boards platform code. Signed-off-by: NEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>
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由 Michal Simek 提交于
Fix my fragments to list all files in the repo. Also fix path to for Xilinx Zynq SoC (mach-zynq) It should be the part of "ARM: zynq: move SoC sources to mach-zynq" (sha1: 0107f240) And cover dts files in board MAINTAINERS files. Reported-by: NHeinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
There is an issue to recognize zynq or zynqmp image because header checking is just the same. That's why zynqmp images are recognized as zynq one. Check unused fields which are initialized to zero in zynq format (__reserved1 0x38 and __reserved2 0x44) which are initialized for zynqmp. This should ensure that images are properly recognized by: ./tools/mkimage -l spl/boot.bin Also show image type as ZynqMP instead of Zynq which is confusing. Reported-by: NAlexander Graf <agraf@suse.de> Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Tested-by: NAlexander Graf <agraf@suse.de>
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This patch adds new command "zynqmp" to handle zynqmp specific commands like "zynqmp secure". This secure command is used for verifying zynqmp specific secure images. The secure image can either be authenticated or encrypted or both encrypted and authenticated. The secure image is prepared using bootgen and will be in xilinx specific BOOT.BIN format. The optional key can be used for decryption of encrypted image if user key was specified while creation BOOT.BIN. Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
ZynqMP Emulation board is no longer tested and there is no reason to keep maintaining it. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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The vcu disable bit in efuse ipdisable register is valid only if PL powered up so, consider PL powerup status for determing EG/EV part. If PL is not powered up, ignore EG/EV part of string. The PL powerup status will be filled by pmufw based on PL PROGB status in the 9th bit of version field. Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Vipul Kumar 提交于
This patch print pl clocks (pl0...pl3) and watchdog clock using clk dump. Signed-off-by: NVipul Kumar <vipulk@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Vipul Kumar 提交于
NAND erase was not happening for size 1GiB or more. Erase command was executing successfully but in actual, it was not erasing. This patch fixed erase issue for 1 GiB or more size nand. Signed-off-by: NVipul Kumar <vipulk@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Use appended dtb which is default option for zynq boards. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
The same command should be used for x16 configuration. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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