LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is re-configured in Bypass mode.
Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

uintptr_t which is a typdef for unsigned long is needed for creating
pointers (32 or 64 bit depending on Core) from 32 bit variables
storing the address.
If a 32 bit variable (u32) is typecasted to a pointer (void *),
compiler gives a warning in case size of pointer on the core is 64 bit.

The typdef has been moved from include/compiler.h to include/linux/types.h
Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

For LS1043, SEC read/writes are made snoopable by setting
the corresponding bits in SCFG to avoid coherency issues.
Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

usec2ticks() function has been defined for ARMv8 which will
be used by SEC Driver.
Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

When reading a large blob. e.g. a linux kernel (several MiBs) a watchdog
timeout might occur meanwhile. So pet the watchdog while operating on
the flash.
Signed-off-by: NAlexander Stein <alexander.stein@systec-electronic.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

MC and debug server are not board-specific. Move reserving memory to SoC
file, using the new board_reserve_ram_top function. Reduce debug server
memory by 2MB to make room for secure memory.

In the system with MC and debug server, the top of u-boot memory
is not the end of memory. PRAM is not used for this reservation.
Signed-off-by: NYork Sun <yorksun@freescale.com>

As the name may be confusing, the CONFIG_SYS_MEM_TOP_HIDE reserves
some memory from the end of ram, tracked by gd->ram_size. It is not
always the top of u-boot visible memory. Rewrite the macro with a
weak function to provide flexibility for complex calcuation. Legacy
use of this macro is still supported.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

DDR has been set as secure in MMU tables. Non-secure master such
as SDHC DMA cannot access data correctly. Mixing secure and non-
secure MMU entries requirs the MMU tables themselves in secure
memory. This patch moves MMU tables into a secure DDR area.

Early MMU tables are changed to set DDR as non-secure. A new
table is added into final MMU tables so secure memory can have
2MB granuality.

gd->secure_ram tracks the location of this secure memory. For
ARMv8 SoCs, the RAM base is not zero and RAM is divided into several
banks. gd->secure_ram needs to be maintained before using. This
maintenance is board-specific, depending on the SoC and memory
bank of the secure memory falls into.
Signed-off-by: NYork Sun <yorksun@freescale.com>

Secure memory is at the end of memory, separated and reserved
from OS, tracked by gd->secure_ram. Secure memory can host
MMU tables, security monitor, etc. This is different from PRAM
used to reserve private memory. PRAM offers memory at the top
of u-boot memory, not necessarily the real end of memory for
systems with very large DDR. Using the end of memory simplifies
MMU setup and avoid memory fragmentation.

"bdinfo" command shows gd->secure_ram value if this memory is
marked as secured.
Signed-off-by: NYork Sun <yorksun@freescale.com>

As the errata A008336 and A008514 do not apply to all LS series SoCs
(such as LS1021A, LS1043A) we move them to an soc specific file
Signed-off-by: NYuan Yao <yao.yuan@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

This is a workaround for hardware erratum.
Write the value of 63b2_0042h to EDDRTQCFG will optimal the
memory controller performance.

The value: 63b2_0042h comes from the hardware team.
Signed-off-by: NYuan Yao <yao.yuan@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Enable snoop and DVM message on all CCI-400 slave ports. Setting
on disabled feature (snoop or DVM) is ignored by CCI-400.
Signed-off-by: NYuan Yao <yao.yuan@freescale.com>
[York Sun: Add commit message]
Reviewed-by: NYork Sun <yorksun@freescale.com>

Enable the IP feature's snoop signal to support
hardware snoop for cache coherence.

SNPCNFGCR contains the bits to drive snoop signal
for various masters.
Signed-off-by: NYuan Yao <yao.yuan@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Create a soc.c file to put the code for soc special settings.
Signed-off-by: NYuan Yao <yao.yuan@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

With gcc-5.x we get a warning about the ambiguity of BUG_ON(!a != b) and
becomes BUG_ON((!a) != b).  In this case reading of the function leads to
us wanting to rewrite this as BUG_ON(a != b).

Cc: Prabhakar Kushwaha <prabhakar@freescale.com>
Cc: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Cc: Haiying Wang <Haiying.Wang@freescale.com>
Cc: Roy Pledge <Roy.Pledge@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

GCC 5.x does not like sizeof(array_variable) and errors out.  Change these
calls to be instead sizeof(u8) (as that's what serdes_prtcl_map is) *
SERDES_PRCTL_COUNT (the number of array elements).

Cc: York Sun <yorksun@freescale.com>
Signed-off-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Remove 115200 from "earlycon" to avoid loss of initial
log messages during linux kernel 4.1  bootup
Signed-off-by: NPratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

This patch also expose the complete DDR region(s) to Linux.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0,
T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on
LS102x Rev2.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

move arch/powerpc/include/asm/fsl_errata.h to include/fsl_errata.h
to make it public for both ARM and POWER SoCs.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: fix soc.h path in fsl_errata.h]
Reviewed-by: NYork Sun <yorksun@freescale.com>

Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

When creating phy-handle property, an unsigned int value is created by
fdt_create_phandle, and memcpy is used to get the value, since DTS is
big endian, the value cannot be used directly on little endian SoCs,
it should be converted by cpu_to_fdt32.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm,
and 2T timing is enabled.
Signed-off-by: NYork Sun <yorksun@freescale.com>

When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm,
and 2T timing is enabled.
Signed-off-by: NYork Sun <yorksun@freescale.com>

In case four chip-selects are all active, the turnaround times need to
increase to avoid overlapping under heavy load.
Signed-off-by: NYork Sun <yorksun@freescale.com>

The workaround requires different setting for range 1 vs 2.
Also adjust timeout value for waiting for controller to be idle.
Signed-off-by: NYork Sun <yorksun@freescale.com>

For four chip-selects enabled case, RTT is parked on all of them.
Signed-off-by: NYork Sun <yorksun@freescale.com>

MR6 bit 6 is set accrodingly for range 1 or 2, per JEDEC spec.
Signed-off-by: NYork Sun <yorksun@freescale.com>

DDR4 has different RTT value and code according to JEDEC spec. Update
the macros and options .
Signed-off-by: NYork Sun <yorksun@freescale.com>

Add xlnx,xps-spi-2.00.a/b which is compatible string
listed in the Linux kernel.
Remove origin one which has no real background.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NJagan Teki <jteki@openedev.com>

Used quite different name's and e-mail address, all of
them mapped to standard name and e-mail address.

Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NJagan Teki <jteki@openedev.com>

Since all spi-flash core operations are moved into
sf_ops.c then it's better to renamed as spi-flash.c
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NJagan Teki <jteki@openedev.com>

Used static for file-scope functions in sf_probe.c
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NJagan Teki <jteki@openedev.com>

Since spi_slave is a spi pointer in spi_flash{} then assign
spi_slave{} pointer to flash->spi and remove spi_slave
pointer argument to
- spi_flash_probe_slave
- spi_flash_scan
Tested-by: NJagan Teki <jteki@openedev.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NJagan Teki <jteki@openedev.com>

For assigning read_bar commands in spansion case, break
is missing this patch add that break.
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NJagan Teki <jteki@openedev.com>

SST parts added on sf_params.c supports both SST_WR which consits
of both BP and WP and there is a spi controller ich which supports
only BP so the relevent _write hook set based on "slave->op_mode_tx"
hence there is no respective change required from flash side hance
removed these.
Tested-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Signed-off-by: NJagan Teki <jteki@openedev.com>

Removed unneeded header includes in sf_ops and sf_probe
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NJagan Teki <jteki@openedev.com>

Using macro's for flash power up read-only access code
leads wrong behaviour hence use idcode0 for runtime
detection, hence the flash which require this functionality
gets detected at runtime.
Tested-by: NJagan Teki <jteki@openedev.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NJagan Teki <jteki@openedev.com>

Most of the register access function are static,
so used simple name to represent each.
Tested-by: NJagan Teki <jteki@openedev.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NJagan Teki <jteki@openedev.com>