Support Driver Model for fsl esdhc driver.

1. Introduce a new structure struct fsl_esdhc_priv
2. Refactor fsl_esdhc_initialize which is originally used by board code.
   - Introduce fsl_esdhc_init to be common usage for DM and non-DM
   - Introduce fsl_esdhc_cfg_to_priv to build the bridge for non-DM part.
   - The original API for board code is still there, but we use
     'fsl_esdhc_cfg_to_priv' and 'fsl_esdhc_init' to serve it.
3. All the functions are changed to use 'struct fsl_esdhc_priv', except
   fsl_esdhc_initialize.
4. Since clk driver is not implemented, use mxc_get_clock to geth
   the clk and fill 'priv->sdhc_clk'.

Has been tested on i.MX6UL 14X14 EVK board:
"
=>dm tree
....
 simple_bus  [ + ]    |   `-- aips-bus@02100000
  mmc        [ + ]    |       |-- usdhc@02190000
  mmc        [ + ]    |       |-- usdhc@02194000
....
=> mmc list
FSL_SDHC: 0 (SD)
FSL_SDHC: 1 (SD)
"
Signed-off-by: NPeng Fan <van.freenix@gmail.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Yangbo Lu <yangbo.lu@nxp.com>
Cc: Hector Palacios <hector.palacios@digi.com>
Cc: Eric Nelson <eric@nelint.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Simon Glass <sjg@chromium.org>
Tested-By: NEric Nelson <eric@nelint.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Enable EFI partition support for ZynqMP.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

PCS auto negotaiation bit should be enabled
along with SGMII autonegotation enabled
in phy.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add support of SGMII to TI phy dp838367
Enable the SGMII and PCS settings in phy
control, CFG2 and BIST registers
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Return error from probe in case of invalid phy address.
This fixes the issue of uboot crash if phy is not detected.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

preboot macro load the uEnv.txt from mmc 0 when bootmode is mmc. uenvcmd is
executed after load of uEnv.txt if it is defined in the uEnv.txt env text
file.

The default importbootenv macro reads the uEnv.txt from mmc.

Additional to this, usb_loadbootenv is added to support loading uEnv.txt
from usb dev 0.
Signed-off-by: NJason Wu <jason.wu.misc@gmail.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Enable FLASH_BAR for these targets to be in sync with all zynq boards.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Initial Ceva Sata init code.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Handle all Xilinx ZynqMP boards with one fragment.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Read information about memory from DT. This patch simplify life with
synchronization between DT and board files.

dram_init() only needs maximum RAM size below 4GB that's why please sort
banks in memory node.
dram_init_banksize() copies memory setup to bi_dram[].
This will avoid reading information from DT twice.

Memory test start/end were changed to DDR location to let memtest still
compiled.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Simplify board config file.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

This option enable adding new platform suport just by adding defconfig
and DTS file which will target generic configuration for SoC.
Make no sense to extend Kconfig just create a pointer between DTS and
configuration file.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Enabling writing files to FAT and EXT4 for USB.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Synchronize it with zynq platform.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Do not use debug() when printing error message. Use printf instead.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

OF_CONTROL is enabled by default that's why this is dead code.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Read information about timer and interrupts from DT. This is the first
small step to move timer and intc to DM.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

There is incorrect setting for USB which didn't work with origin
ps7_init_gpl.X files.
Use default setting for Digilent Zybo projects with HDMI in PL.
Signed-off-by: NMichal Simek <monstr@monstr.eu>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Zybo has on board I2C EEPROM which contains preprogrammed MAC address.
Signed-off-by: NMichal Simek <monstr@monstr.eu>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Provide board specific option how to read MAC address from ROM.
Do it in generic way to be reusable by differnet boards.
If this is not enough board specific functions can be created.

Signed-off-by: Joe Hershberger <joe.hershberger@gmail.com> # driver part
Signed-off-by: NMichal Simek <monstr@monstr.eu>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Enable overwriting variables out of main config file.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

In SGMII cases the isolate bit might set after DMA and
ethernet resets and hence check and clear during
setup_phy if it was set.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Pass appropriate interface type to phy_connect
instead of zero.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add support of Xilinx PCS/PMA core phy for Zynq
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add support of SGMII interface for zynq GEM.
Read xlnx,emio property from DT.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add phy driver support for xilinx PCS/PMA core
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NKedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Patch f8bb6964 (Drop command-processing code when CONFIG_CMDLINE is
disabled) introduced a small typo. This patch fixes it and unbreaks
all boards again that don't have the Hush parser enabled.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>

Armada 375 still has some problems with d-cache enabled in the ethernet
driver (mvpp2). So lets keep the d-cache disabled until this is solved.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>

This patch adds basic support for the Marvell A375 eval board. Tested
are the following interfaces:
- I2C
- SPI
- SPI NOR
- Ethernet (mvpp2), port 0 & 1

Currently the A375 SerDes and DDR3 init code is not intergrated. So
the SPL U-Boot is not fully functional.

Right now, this A375 mainline U-Boot can only be used by chainloading
it via the original Marvell U-Boot. This can be done via this
command:

=> tftpboot 00800000 a375/u-boot-dtb.bin;go 00800000
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>

This patch adds basic support for the Armada 375. Please note that
currently the SerDes and DDR3 init code for the A375 is not
included / enabled. This will be done in a later, follow-up patch.

Right now, this A375 mainline U-Boot can only be used by chainloading
it via the original Marvell U-Boot. This can be done via this
command:

=> tftpboot 00800000 a375/u-boot-dtb.bin;go 00800000
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>

This will be needed by the upcoming Marvell Armada 375 dts files.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>

This patch adds support for the mvpp2 ethernet controller which is integrated
in the Marvell Armada 375 SoC. This port is based on the Linux driver (v4.4),
which has been stripped of the in U-Boot unused portions.

Tested on the Marvell Armada 375 eval board db-88f6720.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Acked-by: NJoe Hershberger <joe.hershberger@gmail.com>

This enables this driver for the Marvell Armada 375 SoC.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviwer-by: NJagan Teki <jteki@openedev.com>

The RTL8211B_driver structure in drivers/net/phy/realtek.c contains a
wrong PHY ID (0x1cc910 instead of 0x1cc912) in the uid field.

The lowest four bits of the PHY ID encode the chip revision (B+C/D/E/F)
of the RTL8211 and the code originally applied a mask of 0xfffff0 to
the PHY ID, so that matching the PHY ID to the appropriate driver code
was only done on the chip type (RTL8211), but not on a specific
revision.

After introduction of support for the RTL8211E, which needed another
startup function than the older chip revisions, commit
42205047 changed the mask to 0xffffff
to make the chip revision relevant for the match, but didn't provide
the now-relevant lower bits of the uid field for the RTL8211B/C.

Fix this by setting the full PHY ID in the RTL8211B_driver uid field.

Fixes: 42205047 ("net/phy: realtek: Fix the PHY ID mask to ensure the correct Realtek PHY is detected")
Signed-off-by: NKarsten Merker <merker@debian.org>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Freescale is now NXP.  I still work there, but I won't be using their
mail system for U-Boot development.
Signed-off-by: NScott Wood <oss@buserror.net>

Call blk_dread, blk_dwrite, blk_derase to ensure that the block cache is
used if enabled and to remove build breakage when CONFIG_BLK is enabled.
Signed-off-by: NEric Nelson <eric@nelint.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Call blk_dread, blk_dwrite, blk_derase to ensure that the block cache is
used if enabled and to remove build breakage when CONFIG_BLK is enabled.
Signed-off-by: NEric Nelson <eric@nelint.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Add a block device cache to speed up repeated reads of block devices by
various filesystems.

This small amount of cache can dramatically speed up filesystem
operations by skipping repeated reads of common areas of a block
device (typically directory structures).

This has shown to have some benefit on FAT filesystem operations of
loading a kernel and RAM disk, but more dramatic benefits on ext4
filesystems when the kernel and/or RAM disk are spread across
multiple extent header structures as described in commit fc0fc50f.

The cache is implemented through a minimal list (block_cache) maintained
in most-recently-used order and count of the current number of entries
(cache_count). It uses a maximum block count setting to prevent copies
of large block reads and an upper bound on the number of cached areas.

The maximum number of entries in the cache defaults to 32 and the maximum
number of blocks per cache entry has a default of 2, which has shown to
produce the best results on testing of ext4 and FAT filesystems.

The 'blkcache' command (enabled through CONFIG_CMD_BLOCK_CACHE) allows
changing these values and can be used to tune for a particular filesystem
layout.
Signed-off-by: NEric Nelson <eric@nelint.com>