Now that warm booting is not supported, there isn't a need for the
BOOTFLAG_COLD and BOOTFLAG_WARM defines, so remove them.

Note that this change makes the board info bd_bootflags field useless.
It will always be set to 0, but we leave it around so that we don't
break the board info structure that some OSes are expecting to be passed
from U-Boot.
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>

Clean up Makefile, and drop a lot of the config.mk files on the way.

We now also automatically pick all boards that are listed in
boards.cfg (and with all configurations), so we can drop the redundant
entries from MAKEALL to avoid building these twice.
Signed-off-by: NWolfgang Denk <wd@denx.de>

The change is currently needed to be able to remove the board
configuration scripting from the top level Makefile and replace it by
a simple, table driven script.

Moving this configuration setting into the "CONFIG_*" name space is
also desirable because it is needed if we ever should move forward to
a Kconfig driven configuration system.
Signed-off-by: NWolfgang Denk <wd@denx.de>

Newer Linux kernels can overrun the initial memory window used for
booting with their BSS area. When this happens, they overwrite the FDT
and silently fail to boot.

On e300 CPUs, the Linux kernel uses an initial BAT covering the first
256MB of RAM. See arch/powerpc/kernel/head_32.S for details. Increase
the value of CONFIG_SYS_BOOTMAPSZ to accommodate the maximum value
allowed by Linux. This will allow very large kernels to boot.
Signed-off-by: NIra W. Snyder <iws@ovro.caltech.edu>
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

This patch removes the completely unused CONFIG_SERIAL_SOFTWARE_FIFO
feature from U-Boot. It has only been implemented for PPC4xx and was not
used at all. So let's remove it and make the code smaller and cleaner.
Signed-off-by: NStefan Roese <sr@denx.de>
Acked-by: NDetlev Zundel <dzu@denx.de>

Some parts that have an Enhanced Local Bus Controller weren't
setting CONFIG_FSL_ELBC.  Fix this so we can use this define
properly going forward (currently it's only used if PHYS_64BIT is
set, which meant not all platforms needed to have it set correctly).
Signed-off-by: NBecky Bruce <beckyb@kernel.crashing.org>
Acked-by: NKim Phillips <kim.phillips@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

before, MPC8349ITX boots u-boot in 4.3sec:

        column1 is elapsed time since first message
        column2 is elapsed time since previous message
        column3 is the message
0.000 0.000: U-Boot 2010.03-00126-gfd4e49c1 (Apr 11 2010 - 17:25:29) MPC83XX
0.000 0.000:
0.000 0.000: Reset Status:
0.000 0.000:
0.032 0.032: CPU:   e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz
0.032 0.000: Board: Freescale MPC8349E-mITX
0.032 0.000: UPMA:  Configured for compact flash
0.032 0.000: I2C:   ready
0.061 0.028: DRAM:  256 MB (DDR1, 64-bit, ECC off, 266.667 MHz)
1.516 1.456: FLASH: 16 MB
2.641 1.125: PCI:   Bus Dev VenId DevId Class Int
2.652 0.011:         00  10  1095  3114  0180  00
2.652 0.000: PCI:   Bus Dev VenId DevId Class Int
2.652 0.000: In:    serial
2.652 0.000: Out:   serial
2.652 0.000: Err:   serial
2.682 0.030: Board revision: 1.0 (PCF8475A)
3.080 0.398: Net:   TSEC1: No support for PHY id ffffffff; assuming generic
3.080 0.000: TSEC0, TSEC1
4.300 1.219: IDE:   Bus 0: .** Timeout **

after, MPC8349ITX boots u-boot in 3.0sec:

0.010 0.010: U-Boot 2010.03-00127-g4b468cc-dirty (Apr 11 2010 - 17:47:29) MPC83XX
0.010 0.000:
0.010 0.000: Reset Status:
0.010 0.000:
0.017 0.007: CPU:   e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz
0.017 0.000: Board: Freescale MPC8349E-mITX
0.038 0.020: UPMA:  Configured for compact flash
0.038 0.000: I2C:   ready
0.038 0.000: DRAM:  256 MB (DDR1, 64-bit, ECC off, 266.667 MHz)
0.260 0.222: FLASH: 16 MB
1.390 1.130: PCI:   Bus Dev VenId DevId Class Int
1.390 0.000:         00  10  1095  3114  0180  00
1.390 0.000: PCI:   Bus Dev VenId DevId Class Int
1.400 0.010: In:    serial
1.400 0.000: Out:   serial
1.400 0.000: Err:   serial
1.400 0.000: Board revision: 1.0 (PCF8475A)
1.832 0.432: Net:   TSEC1: No support for PHY id ffffffff; assuming generic
1.832 0.000: TSEC0, TSEC1
3.038 1.205: IDE:   Bus 0: .** Timeout **

also tested on these boards (albeit with a less accurate
boottime measurement method):

seconds: before  after
8349MDS  ~2.6    ~2.2
8360MDS  ~2.8    ~2.6
8313RDB  ~2.5    ~2.3 #nand boot
837xRDB  ~3.1    ~2.3

also tested on an 8323ERDB.

v2: also remove the delayed icache enablement assumption in arch ppc's
board.c, and add a CONFIG_MPC83xx define in the ITX config file for
consistency (even though it was already being defined in 83xx'
config.mk).
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

because it's convenient.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

and avoid e.g., two identical boards from causing random networking
conflicts when hooked up to the same network.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

There is more and more usage of printing 64bit values,
so enable this feature generally, and delete the
CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL
defines.
Signed-off-by: NHeiko Schocher <hs@denx.de>

some LCRR bits are not documented throughout the 83xx family RMs.
New board porters copying similar board configurations might omit
setting e.g., DBYP since it was not documented in their SoC's RM.

Prevent them bricking their board by retaining power on reset values
in bit fields that the board porter doesn't explicitly configure
via CONFIG_SYS_<registername>_<bitfield> assignments in the board
config file.

also move LCRR assignment to cpu_init_r[am] to help ensure no
transactions are being executed via the local bus while CLKDIV is being
modified.

also start to use i/o accessors.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

linux mpc83xx_defconfig kernels are getting bigger, accommodate for
their growth by adjusting default load and fdt addresses.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

when using Linus' 83xx_defconfig, the mpc8377rdb would hang at boot
at either:

NET: Registered protocol family 16

or the

io scheduler cfq registered

message.  Fixing up these DDR settings appears to fix the problem.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

Signed-off-by: NWolfgang Denk <wd@denx.de>

This patch adds support for eSDHC on MPC837XERDB boards. The WP
switch doesn't seem to work on RDB boards though, the WP pin is
always asserted (can see the pin state when it's in GPIO mode).

FSL DR USB and FSL eSDHC are mutually exclusive because of pins
multiplexing, so user should specify 'esdhc' or 'dr_usb' options
in the hwconfig environment variable to choose between the
devices.

p.s.
Now we're very close to a monitor len limit (196 bytes left using
gcc-4.2.0), so also increase the monitor len by one sector (64 KB).
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Acked-by: NKim Phillips <kim.phillips@freescale.com>

Saving the environment leads to overwriting u-boot itself,
bricking boards.  Increase u-boot's image size so the environment
base address doesn't end up overlapping u-boot text.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

Use the standard lowercase "x" capitalization that other Freescale
architectures use for CPU defines to prevent confusion and errors
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

Use the standard lowercase "xx" capitalization that other Freescale
architectures use for CPU defines to prevent confusion and errors
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

On MPC8377E-RDB and MPC8378E-RDB boards we have PCIe and mini-PCIe
slots. Let's support them.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

The CONFIG_CMD_ENV option controls enablement of the `saveenv` command
rather than a generic "env" command, or anything else related to the
environment.  So, let's make sure the define is named accordingly.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Currently this is not creating any problem. But it will result
in compilation error when used as below.

printf("CFG_SDRAM_CFG2 - %08x\n", CFG_SDRAM_CFG2);
Signed-off-by: NSelvamuthukumar <selva.muthukumar@e-coninfotech.com>

continuation of the theme based on git grep "^#define CFG_.*;$" include/
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

bootdelay set to -1 'permanently' disables autobooting, even if
bootcmd is specified.  Change to a positive value to allow
autobooting when a bootcmd is set.
Reported-by: NCoray Tate <Coray.Tate@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

the operating system may leave flash in a h/w locked state after writing.
This allows u-boot to continue to write flash by enabling h/w unlocking
by default.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

rename CFG_FLASH_CFI_DRIVER to CONFIG_FLASH_CFI_DRIVER
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Change all code that conditionally operates on high bat
registers (that is, BATs 4-7) to look at CONFIG_HIGH_BATS
instead of the myriad ways this is done now.  Define the option
for every config for which high bats are supported (and
enabled by early boot, on parts where they're not always
enabled)
Signed-off-by: NBecky Bruce <becky.bruce@freescale.com>

this seems as a good compromise between human memory, typing,
and last but not least, to accommodate for current and future kernel bloat.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
Acked-by: NDave Liu <daveliu@freescale.com>

Currently the SATA controller clock is configured as CSB clock,
usually the CSB clock is 400/333/266MHz.

However, The SATA IP block is only guaranteed to operate up to
200 MHz as stated in the HW spec.

The bug is reported by Joe D'Abbraccio <ljd015@freescale.com>

This patch makes the SATA clock as half of CSB clock.
Signed-off-by: NDave Liu <daveliu@freescale.com>
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

Linux understands "host" (default), "peripheral" and "otg" (broken).
Though, U-Boot doesn't restrict dr_mode variable to these values (think
of renames in future).
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

The device trees for these boards describe PCI I/O as starting from
address zero from the device's perspective.

Placing I/O elsewhere may cause problems with certain PCI boards, and may
cause problems with Linux.
Signed-off-by: NScott Wood <scottwood@freescale.com>

This is primarily for the early console support.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>

On the MPC8377ERDB: 2 SATA and 2 PCI-E.
On the MPC8378ERDB: 2 PCI-E
On the MPC8379ERDB: 4 SATA
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>

Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>

Update the MPC8349E-mITX, MPC8313E-RDB, and MPC837XE-RDB board files to upload
the Vitesse VSC7385 firmware.  Changed CONFIG_VSC7385 to CONFIG_VSC7385_ENET.
Cleaned up the board header files to make selecting the VSC7385 easier to
control.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

the dts file basenames were updated in linux - this helps avoid
inadvertently loading any old dtbs laying around.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>