Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>

Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>

This merges the CRC16-CCITT headers into u-boot/crc.h to prepare for
rolling CRC16 into the hash infrastructure.  Given that CRC8, CRC32
and CRC32-C already have their prototypes in a single header file, it
seems a good idea to also include CRC16-CCITT in the same.
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

LX2160A Soc is based on Layerscape Chassis Generation 3.2
architecture with features:
 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC,
 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers,
 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs,
 4 TZASC instances, etc.

SoC personalites:
LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs
LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs
Signed-off-by: NBao Xiaowei <xiaowei.bao@nxp.com>
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: NMeenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: NVabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: NSriram Dash <sriram.dash@nxp.com>
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Adds TFABOOT support and allows to pick FMAN firmware
on basis of boot source.
Signed-off-by: NPankit Garg <pankit.garg@nxp.com>
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>
[YS: fix checkpatch issues]
Reviewed-by: NYork Sun <york.sun@nxp.com>

We cannot be sure that the interface name takes up the full length of the
space available to it. Use strcpy() instead of memcpy() in this case. This
corrects a valgrind warning.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This patch throws an error if 64-bit support is expected
but DMA hardware is not capable of 64-bit support. It also
prints a debug message if DMA is capable of 64-bit but not
using it.
Signed-off-by: NSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Signed-off-by: NMichal Simek <monstr@monstr.eu>

This patch adds 64-bit addressing support for zynq gem.
This means it can perform send and receive operations on
64-bit address buffers.
Signed-off-by: NVipul Kumar <vipul.kumar@xilinx.com>
Signed-off-by: NSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Signed-off-by: NMichal Simek <monstr@monstr.eu>

Remove spi_init definition which never used on
respective code since from many years.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

Add the compatible string for the upcoming Amlogic AXG SoC family.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>

Add the compatible string for the Amlogic GXBB SoC family.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>

Some boards have the EMAC TX/RX lanes wired with a different length with
the clock lane, which can be workarounded by setting a TX/RX delay in
the EMAC.

This kind of delays are already defined in the newest device tree
binding of dwmac-sun8i, which has already entered linux-next.

Add support for setting these delays.
Signed-off-by: NIcenowy Zheng <icenowy@aosc.io>
Reviewed-by: NJagan Teki <jagan@openedev.com>

Update TI Keystone 2 driver to re-use common mdio lib.
Reviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com>

Update TI CPSW driver to re-use common mdio lib
Reviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com>

All existing TI SoCs network HW have similar MDIO implementation, so
introduce common mdio support library which can be reused by TI networking
drivers.
Reviewed-by: NTom Rini <trini@konsulko.com>
Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Update to use SPDX license identifier.
Reviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com>

Networking support for all TI K2 boards converted to use DM model and
CONFIG_DM_ETH enabled in all corresponding defconfig files, hence drop
unused non DM K2 networking code.
Reviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com>

Convert DRIVER_TI_KEYSTONE_NET to Kconfig.
Reviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com>

Add drivers/net/ti/ folder and move all TI's code in this folder for better
maintenance.
Reviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com>

The VSC8574 PHY is a 4-port PHY that is 10/100/1000BASE-T, 100BASE-FX,
1000BASE-X and triple-speed copper SFP capable, can communicate with
the MAC via SGMII, QSGMII or 1000BASE-X, supports WOL, downshifting and
can set the blinking pattern of each of its 4 LEDs, supports SyncE as
well as HP Auto-MDIX detection.

This adds support for 10/100/1000BASE-T and SGMII/QSGMII link with the
MAC.

The VSC8574 has also an internal Intel 8051 microcontroller whose
firmware needs to be patched when the PHY is reset. If the 8051's
firmware has the expected CRC, its patching can be skipped. The
microcontroller can be accessed from any port of the PHY, though the CRC
function can only be done through the PHY that is the base PHY of the
package (internal address 0) due to a limitation of the firmware.

The GPIO register bank is a set of registers that are common to all PHYs
in the package. So any modification in any register of this bank affects
all PHYs of the package.
Signed-off-by: NQuentin Schulz <quentin.schulz@bootlin.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Part of the config is common between the VSC8584 and the VSC8574, so to
prepare for the upcoming support of VSC8574, use the phy_device.priv
pointer that will keep the function that holds code that is PHY-specific
and that should be called during config function.
Signed-off-by: NQuentin Schulz <quentin.schulz@bootlin.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

The VSC8584 PHY is a 4-port PHY that is 10/100/1000BASE-T, 100BASE-FX,
1000BASE-X and triple-speed copper SFP capable, can communicate with the
MAC via SGMII, QSGMII or 1000BASE-X, supports downshifting and can set
the blinking pattern of each of its 4 LEDs, supports hardware offloading
of MACsec and supports SyncE as well as HP Auto-MDIX detection.

This adds support for 10/100/1000BASE-T and SGMII/QSGMII link with the
MAC.

The VSC8584 has also an internal Intel 8051 microcontroller whose
firmware needs to be patched when the PHY is reset. If the 8051's
firmware has the expected CRC, its patching can be skipped. The
microcontroller can be accessed from any port of the PHY, though the CRC
function can only be done through the PHY that is the base PHY of the
package (internal address 0) due to a limitation of the firmware.

The GPIO register bank is a set of registers that are common to all PHYs
in the package. So any modification in any register of this bank affects
all PHYs of the package.

The revA of the VSC8584 PHY (which is not and will not be publicly
released) should NOT patch the firmware of the microcontroller or it'll
make things worse, the easiest way is just to not support it.
Signed-off-by: NQuentin Schulz <quentin.schulz@bootlin.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

The Faraday ftgmac100 MAC controllers as found on the Aspeed SoCs have
some slight differences in the HW interface (End-Of-Rx/Tx-Ring bits).
Signed-off-by: NCédric Le Goater <clg@kaod.org>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NJoel Stanley <joel@jms.id.au>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Signed-off-by: NCédric Le Goater <clg@kaod.org>
Reviewed-by: NJoel Stanley <joel@jms.id.au>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Signed-off-by: NCédric Le Goater <clg@kaod.org>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Use simple arrays under the device priv structure to hold the RX and
TX descriptors and handle memory coherency by invalidating or flushing
the d-cache when required.
Signed-off-by: NCédric Le Goater <clg@kaod.org>
Reviewed-by: NJoel Stanley <joel@jms.id.au>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Implement the MDIO bus read/write functions using the readl_poll_timeout()
routine, initialize the bus and scan for the PHY. RGMII and RMII mode
are supported.
Signed-off-by: NCédric Le Goater <clg@kaod.org>
Reviewed-by: NJoel Stanley <joel@jms.id.au>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Signed-off-by: NCédric Le Goater <clg@kaod.org>
Reviewed-by: NJoel Stanley <joel@jms.id.au>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

The driver is based on the previous one and the code is only adapted
to fit the driver model. The support for the Faraday ftgmac100
controller is the same with MAC and MDIO bus support for RGMII/RMII
modes.

Configuration is updated to enable compile again. At this stage, the
driver compiles but is not yet functional.
Signed-off-by: NCédric Le Goater <clg@kaod.org>
Reviewed-by: NJoel Stanley <joel@jms.id.au>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Signed-off-by: NCédric Le Goater <clg@kaod.org>
Reviewed-by: NJoel Stanley <joel@jms.id.au>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Signed-off-by: NCédric Le Goater <clg@kaod.org>
Reviewed-by: NJoel Stanley <joel@jms.id.au>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

This patch adds ethernet support for the MIPS based Mediatek MT76xx SoCs
(e.g. MT7628 and MT7688), including a minimum setup of the integrated
switch. This driver is loosly based on the driver version included in
this MediaTek github repository:

https://github.com/MediaTek-Labs/linkit-smart-uboot.git

Tested on the MT7688 LinkIt smart-gateway and on the
Gardena-smart-gateway.
Signed-off-by: NStefan Roese <sr@denx.de>
Reviewed-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Frank Wunderlich <frankwu@gmx.de>
Cc: Weijie Gao <hackpascal@gmail.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Per T1040RM (Rev. 1, 08/2015), there are 2 issues with the RCW EC2
settings.

- The value of FSL_CORENET_RCWSR13_EC2_FM1_GPIO is wrong and should
  be 0x04000000 (value of 1 in RCW bit [420:421])
- Value of 2/3 are reserved in RCW bit [420:421], hence there is no
  macro FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NPoonam Aggrwal <poonam.aggrwal@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Complete in the drivers directory the work started with
commit 83d290c5 ("SPDX: Convert all of our single
license tags to Linux Kernel style").
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

Add compatible property and enable the FEC ipg clock when probing
on i.MX8X. Add specific function for reading FEC clock rate via
clock driver when configuring MII speed register. Allow FEC_MXC
selection for i.MX8.
Signed-off-by: NAnatolij Gustschin <agust@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

The default Linux PHY reset delay is 10ms. This is also the requirement
for Marvell 88E151x PHYs, which are likely to be used with this Ethernet
MAC.

Cc: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: NBaruch Siach <baruch@tkos.co.il>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Reviewed-by: NStefan Roese <sr@denx.de>

The dm_gpio_set_value() call sets the logical level of the GPIO signal.
That is, it takes the GPIO_ACTIVE_{LOW,HIGH} property into account. The
driver needs to assert the reset, and then deassert it. Not the other
way around.

Cc: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: NBaruch Siach <baruch@tkos.co.il>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Reviewed-by: NStefan Roese <sr@denx.de>

The DT property "phy-mode" already provides the transceiver type.
Use it so that we do not have to also set CONFIG_FEC_XCV_TYPE
Signed-off-by: NMartin Fuzzey <martin.fuzzey@flowbird.group>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Configure the phy regulator if defined by the "phy-supply" DT phandle.
Signed-off-by: NMartin Fuzzey <martin.fuzzey@flowbird.group>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

The DT binding says:
- phy-reset-duration : Reset duration in milliseconds.  Should present
  only if property "phy-reset-gpios" is available.  Missing the property
  will have the duration be 1 millisecond.  Numbers greater than 1000 are
  invalid and 1 millisecond will be used instead.

However the current code:
 - clamps values greater than 1000ms to 1000ms rather than 1.
 - does not initialize the delay if the property does not exist
   (else clause mismatch)
 - returns an error if phy-reset-gpios is not defined

Fix all this and simplify by using dev_read_u32_default()
Signed-off-by: NMartin Fuzzey <martin.fuzzey@flowbird.group>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>