- 23 11月, 2016 7 次提交
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由 Thomas Abraham 提交于
Remove the custom low-level initialization function and reuse the default low-level initialization function. But this requires the ARMV8_MULTIENTRY config option to be enabled for Exynos7420. On Exynos7420, the boot CPU belongs to the second cluster and so with ARMV8_MULTIENTRY config option enabled, the 'branch_if_master' macro fails to detect the CPU as boot CPU. As a temporary workaround the CPU_RELEASE_ADDR is set to point to '_main'. Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Alison Wang <alison.wang@nxp.com> Signed-off-by: NThomas Abraham <thomas.ab@samsung.com> Reviewed-by: NAlison Wang <alison.wang@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Priyanka Jain 提交于
NXP ARMv8 SoC LS2080A release all secondary cores in one-go. But other new SoCs like LS2088A, LS1088A release secondary cores one by one. Update code to release secondary cores based on SoC SVR Add code to release cores one by one for non LS2080A SoCs Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com> Signed-off-by: NRaghav Dogra <raghav.dogra@nxp.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: remove "inline" from declaration of initiator_type] Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Priyanka Jain 提交于
The QorIQ LS2088A SoC is built on layerscape architecture. It is similar to LS2080A SoC with some differences like 1)Timer controller offset is different 2)It has A72 cores 3)It supports TZASC module Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Priyanka Jain 提交于
LS2080 SoC and its personalities does not support TZASC But other new SoCs like LS2088A, LS1088A supports TZASC Hence, skip initializing TZASC for Ls2080A based on SVR Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Priyanka Jain 提交于
TZASC registers like TZASC_GATE_KEEPER, TZASC_REGION_ATTRIBUTES are 32-bit regsiters. So while doing register load-store operations, 32-bit intermediate register, w0 should be used. Update x0 register to w0 register type. Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Priyanka Jain 提交于
Timer controller base address has been changed from LS2080A SoC (and its personalities) to new SoCs like LS2088A, LS1088A. Use SVR based timer base address detection to avoid compile time #ifdef. Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Priyanka Jain 提交于
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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- 22 11月, 2016 13 次提交
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由 Shengzhou Liu 提交于
Update CONFIG_LS2080A to CONFIG_FSL_LSCH3 to make those workaround implementing of erratum reusable for more SoCs. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Yuan Yao 提交于
Signed-off-by: NYuan Yao <yao.yuan@nxp.com> [YS: Reviese commit subject] Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Yuan Yao 提交于
Change core clock to 1.2GHz in the configurations for SD and NAND boot. Signed-off-by: NYuan Yao <yao.yuan@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Shaohui Xie 提交于
The current value to check whether the PHY was configured has dependency on MC, it expects MC to start PCS AN, this is not true during boot up, so it should be changed to remove the dependency. The PHY's register space should be restore to default after accessing extended space. Signed-off-by: NShaohui Xie <Shaohui.Xie@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Hou Zhiqiang 提交于
This deadloop is introduced by commit: 71fe2225 fsl: serdes: ensure accessing the initialized maps of serdes protocol deadloop detail: cpu_init_r => fsl_serdes_init => p4080_erratum_serdes_a005 => is_serdes_configured => fsl_serdes_init Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Sriram Dash 提交于
Defines get_svr() for mpc512x devices Signed-off-by: NSriram Dash <sriram.dash@nxp.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Priyanka Jain 提交于
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Priyanka Jain 提交于
Add these serdes protocols Serdes1: 0x39, 0x4B, 0x4C, 0x4D Serdes2: 0x47, 0x57 Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com> [YS: Revise commit message] Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Shaohui Xie 提交于
LPUART0 is used by default, and it's using platform clock. Signed-off-by: NShaohui Xie <Shaohui.Xie@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Shaohui Xie 提交于
It's not always true that LPUART clock is CONFIG_SYS_CLK_FREQ. This patch provides a weak function get_lpuart_clk(), so that the clock can be ovreridden on a specific board which uses different clock for LPUART. Signed-off-by: NShaohui Xie <Shaohui.Xie@nxp.com> [YS: Reformat commit message] Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Feng Li 提交于
The patch adds support for Freescale ls1021a-iot board. Signed-off-by: NFeng Li <feng.li_2@nxp.com> [YS: rewrite commit message, fix whitespace in Kconfig] Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Yuan Yao 提交于
There is the stmicro DSPI flash on LS12080ARDB. Enable DSPI flash related configure options. Signed-off-by: NYuan Yao <yao.yuan@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Pratiyush Srivastava 提交于
Add optimization parameters like "quiet" in bootargs to reduce the system boot time Signed-off-by: NPratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: NHarninder Rai <harninder.rai@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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- 19 11月, 2016 2 次提交
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由 Semen Protsenko 提交于
This option isn't used for anything, so get rid of it. Signed-off-by: NSam Protsenko <semen.protsenko@linaro.org>
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由 Semen Protsenko 提交于
Signed-off-by: NSam Protsenko <semen.protsenko@linaro.org> [trini: Fix sniper and kc1 migration] Signed-off-by: NTom Rini <trini@konsulko.com>
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- 18 11月, 2016 2 次提交
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git://github.com/agraf/u-boot由 Tom Rini 提交于
Patch queue for efi - 2016-11-17 Highlights this time around: - x86 efi_loader support - hello world efi test case - network device name is now representative - terminal output reports modes correctly - fix psci reset for ls1043/ls1046 - fix efi_add_runtime_mmio definition for x86 - efi_loader support for ls2080
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- 17 11月, 2016 8 次提交
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由 Alexander Graf 提交于
Most new systems in U-Boot these days make use of the generic "distro" framework which allows a user to have U-Boot scan for a bootable OS on all available media types. This patch extends the LS2080ARDB board to use that framework if the hard coded NOR flash location does not contain a bootable image. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
When implementing efi loader support, we can expose runtime services for payloads. One such service is CPU reset. This patch implements RTS CPU reset support for layerscape systems. Signed-off-by: NAlexander Graf <agraf@suse.de> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Alexander Graf 提交于
The efi loader code has its own memory map, so it needs to be aware where the spin tables are located, to ensure that no code writes into those regions. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
The DP-DDR shouldn't be exposed as conventional memory to an OS, so let's rather claim it's a reserved region in the EFI memory map Signed-off-by: NAlexander Graf <agraf@suse.de> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Alexander Graf 提交于
On ls2080 we have a separate network fabric component which we need to shut down before we enter Linux (or any other OS). Along with that also comes configuration of the fabric using a description file. Today we always stop and configure the fabric in the boot script and (again) exit it on device tree generation. This works ok for the normal booti case, but with bootefi the payload we're running may still want to access the network. So let's add a new fsl_mc command that defers configuration and stopping the hardware to when we actually exit U-Boot, so that we can still use the fabric from an EFI payload. For existing boot scripts, nothing should change with this patch. Signed-off-by: NAlexander Graf <agraf@suse.de> Reviewed-by: NYork Sun <york.sun@nxp.com> [agraf: Fix x86 build]
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由 Alexander Graf 提交于
The efi_add_runtime_mmio prototype for disabled CONFIG_EFI_LOADER was different from the enabled one. Sync them. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
The NXP ls1043 and ls1046 systems do not (yet) have PSCI enablement for reset. Don't enable generic PSCI reset code on them. Signed-off-by: NAlexander Graf <agraf@suse.de>
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由 Alexander Graf 提交于
Some boards decided not to run ATF or other secure firmware in EL3, so they instead run U-Boot there. The uEFI spec doesn't know what EL3 is though - it only knows about EL2 and EL1. So if we see that we're running in EL3, let's get into EL2 to make payloads happy. Signed-off-by: NAlexander Graf <agraf@suse.de> Reviewed-by: NYork Sun <york.sun@nxp.com>
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- 16 11月, 2016 4 次提交
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由 Maxime Ripard 提交于
The SinA33 comes with an optional 7" display. Enable it in the configuration. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: NHans de Goede <hdegoede@redhat.com>
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由 Maxime Ripard 提交于
The SinA33 has an 4GB Toshiba eMMC connected to the MMC2 controller. Enable it. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: NChen-Yu Tsai <wens@csie.org> Reviewed-by: NHans de Goede <hdegoede@redhat.com>
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由 Maxime Ripard 提交于
The sun8i SoCs also have a 8 bits capable MMC2 controller. Enable the support for those too. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: NChen-Yu Tsai <wens@csie.org> Reviewed-by: NHans de Goede <hdegoede@redhat.com>
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由 Maxime Ripard 提交于
Some eMMC will fail at the first switch, but would succeed in a subsequent one. Make sure we try several times to cover those cases. The number of retries (and the behaviour) is currently what is being used in Linux. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: NHans de Goede <hdegoede@redhat.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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- 15 11月, 2016 4 次提交
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由 Bharat Kumar Gogada 提交于
Adding prefetchable memory space to pcie device tree node. Shifting configuration space to 64-bit address space. Removing pcie device tree node from amba as it requires size-cells=<2> in order to access 64-bit address space. Signed-off-by: NBharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Kedareswara rao Appana 提交于
Zynqmp DMA driver expects two clocks (main clock and apb clock) For LPDDMA channels the two clocks are missing in the Dma node resulting probe failure. xilinx-zynqmp-dma ffa80000.dma: main clock not found. xilinx-zynqmp-dma ffa80000.dma: Probing channel failed xilinx-zynqmp-dma: probe of ffa80000.dma failed with error -2 This patch fixes this issue. Signed-off-by: NKedareswara rao Appana <appanad@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Kedareswara rao Appana 提交于
LPDDMA default allows only secured access. inorder to enable these dma channels, one should ensure that it allows non secure access. This patch updates the same. Reported-by: NSai Pavan Boddu <saipava@xilinx.com> Signed-off-by: NKedareswara rao Appana <appanad@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Use 64bit size cell for main amba bus instead of 32bit because PCIe node requires it Change 64bit sizes also for all others IPs. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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