- 13 8月, 2017 40 次提交
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由 Kever Yang 提交于
mmc using 150000000 as max-frequency like what rk3288 sets. This can speed up the mmc read/write, the actual mmc clock is: Before this patch: 37.125M After this patch: 49.5M Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Kever Yang 提交于
add node for sdmmc in dts and rk3229-evb. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Philipp Tomsich 提交于
Moving SPL_LDSCRIPT to Kconfig triggered an unfortunate attempt of command substitution, as the sourced auto.conf may include $(ARCH) which tries to execute a command 'ARCH'. This showed up as a warning similar to the following: include/config/auto.conf: line 209: ARCH: command not found This change does no longer attempt to source auto.conf, but rather passes it through awk to retrieve the values for CONFIG_LOCALVERSION and CONFIG_LOCALVERSION_AUTO. This will also mitigate the risk of unintended command substitution. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reported-by: NAndy Yan <andy.yan@rock-chips.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NKlaus Goger <klaus.goger@theobroma-systems.com> Reviewed-by: NJakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
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由 Kever Yang 提交于
Disable the ddr secure region setting in SPL and the ddr memory becomes non-secure, every one can access it. the trust firmware like OPTEE should have the correct setting for it after SPL if there is one. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Kever Yang 提交于
It should be '<<' instead of '<' for _MASK definition, fix it. Signed-off-by: NZiyuan Xu <xzy.xu@rock-chips.com> Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
With the new way of doing things (i.e. the hierarchical selection of SPL_LDSCRIPT via Kconfig) in place, this moves the SPL_LDSCRIPT setting for the RK3368 from defconfig back into Kconfig. With this done, there should be no lingering cases of SPL_LDSCRIPT outside of Kconfig files. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
With the hierarchical defaults set up, we remove these from the header files. To do so, I've run moveconfig on SPL_LDSCRIPT and this commits the changes. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
With SPL_LDSCRIPT moved to Kconfig (and this being a 'string' config node), all the lingering definitions in header files will cause warnings/errors due to the redefinition of the configuration item. As we don't want to pollute the defconfig files (and values should usually be identical for entire architectures), the defaults are moved into Kconfig. Kconfig will always pick the first default that matches, so please keep these values at the end of each file (to allow any board-specific Kconfig, which will be included earlier) to override with an unconditional default setting. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
With the changes to split SPL/TPL for the RK3368, I apparently missed some needed adjustments to the RK3188 Kconfig and rock_defconfig. This fixes build-issues for the rock board after applying the RK3368 enablement (and SPL/TPL) set that resulted from TPL_SERIAL_SUPPORT, TPL_ROCKCHIP_BACK_TO_BROM and TPL_TINY_MEMSET being separate symbols now. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Andy Yan 提交于
As the debug uart is marked as dm-pre-reloc, the pinctrl driver will handle the correct iomux setting. Signed-off-by: NAndy Yan <andy.yan@rock-chips.com> Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Andy Yan 提交于
The default 1kb pre-reloc malloc pool is not enough for dm core to enable the dm-pre-reloc device drivers. Signed-off-by: NAndy Yan <andy.yan@rock-chips.com> Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Andy Yan 提交于
Device drivers like debug serial, dmc should be enabled before relocation, so add u-boot.dtsi files to contain devices that should be marked as dm-pre-reloc. Signed-off-by: NAndy Yan <andy.yan@rock-chips.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
When using DM timers w/ the timer0 block within the RK3368, we no longer depend on the ARMv8 generic timer counting. This allows us to drop the secure timer initialisation from the TPL and SPL stages. The secure timer will later be set up by ATF, which starts the ARMv8 generic timer. Thus, there will be a dependency from Linux to the ATF through the ARMv8 generic timer... this seems reasonable, as Linux will require the ATF (and PSCI) to start up the secondary cores anyway (in other words: we don't add any new dependencies). Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
There is no reasonably robust way (this will be needed so early that diagnostics will be limited) to specify the base-address of the secure timer through the DTS for TPL and SPL. In order to allow us a cleaner way to structure our SPL and TPL stage, we now move to a DM timer driver. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
To use it with the DM timer driver in SPL and TPL, timer0 needs to be marked as pre-reloc. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
This adds a device-model driver for the timer block in the RK3368 (and similar devices that share the same timer block, such as the RK3288) for the down-counting (i.e. non-secure) timers. This allows us to configure U-Boot for the RK3368 in such a way that we can run with the secure timer inaccessible or uninitialised (note that the ARMv8 generic timer does not count, if the secure timer is not enabled). Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
To fully support DM timer in SPL and TPL, we need a few things cleaned up and normalised: - inclusion of the uclass and drivers should be an all-or-nothing decision for each stage and under control of $(SPL_TPL_)TIMER instead of having the two-level configuration with TIMER and $(SPL_TPL_)TIMER_SUPPORT - when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can not be compiled in This normalises configuration to $(SPL_TPL_)TIMER and moves the config options to drivers/timer/Kconfig (and cleans up the collateral damage to some defconfigs that had SPL_TIMER_SUPPORT enabled). Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
The timer-uclass depends on full OF_CONTROL through its interrogation of /chosen and the code to determine the clock-frequency. For the OF_PLATDATA case, these code-paths are disabled and it becomes the timer driver's responsibility to correctly set the clock-frequency in the uclass priv-data. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
Splitting the feature selection for SPL and TPL, caused a few build failures to mpx85xx boards. This fixes the fallout by adding the needed new option names to the respective defconfig files. Signed-off-byL Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Klaus Goger 提交于
prefix the bl31 firmware needed to build uboot.itb so it can coexist in the build area with ATFs from other boards (i.e. lion_rk3368) Signed-off-by: NKlaus Goger <klaus.goger@theobroma-systems.com> Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
The ITS file generated warnings due to @<num> designations in the naming which cause DTC to complain as follows: Warning (unit_address_vs_reg): Node /images/uboot@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /images/atf@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /images/pmu@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /images/fdt@1 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /configurations/conf@1 has a unit name, but no reg property This removes the @<num> part from the names, as we only have a single image for each payload aspect (and only a single configuration) anyway. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
We can finally drop TPL_STACK, TPL_TEXT_BASE and TPL_MAX_SIZE off the whitelist (this time it's really happening!) and migrate the setting (only used on the RK3368-uQ7 so far) into Kconfig. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
The RK3368 needs to have a different base-address and stack-pointer for its TPL stage. Now that we want to do this via Kconfig, we need to tick the appropriate 'TPL_NEEDS_...' boxes. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
Now that TPL_STACK has been moved off the whitelist (ok, I'm lying: the 'moving off the whitelist' part comes in once moveconfig runs... which will be a few commits down the line) and added to Kconfig, we need to test CONFIG_TPL_NEEDS_SEPARATE_STACK to see whether the value from TPL_STACK should be used or whether we try to inherit whatever SPL uses. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
Let's clean up behind ourselves and move the (newly defined) TPL_STACK, TPL_MAX_SIZE and TPL_TEXT_BASE into Kconfig. Given that 0x0 might be considered to be valid values for TPL_TEXT_BASE and TPL_STACK, we need to introduce helper config options ("TPL_NEEDS_SEPARATE_...") to indicate that these symbols are used (and not inherited from their SPL variants) for any given target-platform. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
Set TPL_LDSCRIPT in Kconfig, so we don't have to pollute our header file. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Philipp Tomsich 提交于
Now that we have split up SPL_LDSCRIPT into a SPL and TPL variant and have started to use the TPL-variant for the RK3368, it's time to clean up behind ourselves: move both variants into Kconfig and remove them from the whitelist. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
The RK3368-uQ7 (codenamed 'Lion') is a micro-Qseven (40mm x 70mm, MXM-230 edge connector compatible with the Qseven specification) form-factor system-on-module based on the octo-core Rockchip RK3368. It is designed, supported and manufactured by Theobroma Systems. It provides the following features: - 8x Cortex-A53 (in 2 clusters of 4 cores each) - (on-module) up to 4GB of DDR3 memory - (on-module) SPI-NOR flash - (on-module) eMMC - Gigabit Ethernet (with an on-module KSZ9031 PHY) - USB - HDMI - MIPI-DSI/single-channel LVDS (muxed on the 'LVDS-A' pin-group) - various 'slow' interfaces (e.g. UART, SPI, I2C, I2S, ...) Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
For the RK3368, we can reuse the SPI driver (although we'll have to eventually investigate whether it can be merged with the designware_spi.c driver) also used for the RK3288 and RK3399. This adds the necessary compatible string to support the RK3368. Note that the assumption that GPLL will be clocked at 594MHz is not true for the RK3368, but this will not lead to incorrect functioning (just to a lower-than-expected SPI operating frequency): this has been documented in the driver, so it doesn't cause any headaches when someone next needs to touch the clock code of this driver. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
With SPL and TPL support for the RK3368 in place, mark SPL and TPL as supported from Kconfig for the RK3368. As this is primarily tested on the RK3368-uQ7, we'll leave it to board's individual defconfig to enable. Also enable DEBUG_UART_BOARD_INIT for the RK3368, so we get output during the early boot-up, as we turn on TPL and SPL. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
Adds SPL support for the RK3368 (assuming that our TPL stage has initialised DRAM and set up the memory firewall). Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
In order to reuse the support for the u-boot,spl-boot-order property from the rk3399, we split it into a reusable module that can be included by the SPL code for any of our boards. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
This adds the TPL support for the RK3368, including the u-boot-tpl.lds. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
To build TPL and SPL stages for the RK3368, we will also need to enable the SPL_FRAMEWORK. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
For full SPL support, including DRAM initialisation, we need a few nodes from the DTS: this commit adds the DMC (DRAM controller) node, the service_msch (memory scheduler) node and marks GRF, PMUGRF and CRU as 'u-boot,dm-pre-reloc'. In addition to this, we also include the dt-binding for the DMC to allow DTS files including this DTSI to refer to the symbolic constants for the DDR3 bin and for the memory-schedule. Note that the DMC contains both the memory regions for the (Designware) protocol controller as well as the DDR PHY. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
This adds a DRAM controller driver for the RK3368 and places it in drivers/ram/rockchip (where the other DM-enabled DRAM controller drivers for rockchip devices should also be moved eventually). At this stage, only the following feature-set is supported: - DDR3 - 32-bit configuration (i.e. fully populated) - dual-rank (i.e. no auto-detection of ranks) - DDR3-1600K speed-bin This driver expects to run from a TPL stage that will later return to the RK3368 BROM. It communicates with later stages through the os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR init code). Unlike other DMC drivers for RK32xx and RK33xx parts, the required timings are calculated within the driver based on a target frequency and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this time). The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0) register for controlling the operation of its (single-channel) DRAM controller in the GRF block. This provides for selecting DDR3, mobile DDR modes, and control low-power operation. As part of this change, DDRC0_CON0 is also added to the GRF structure definition (at offset 0x600). Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
Handling TPL and SPL in the Makefile for mach-rockchip was based on nested if checks and/or if-else-if paths. This can be simplified and made more readable by using $(SPL_TPL_) and by introducing intermediate variables for the aggregation of SPL and TPL features. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
The GMAC in the RK3368 once again is identical to the incarnation in the RK3288 and the RK3399, except for where some of the configuration and control registers are located in the GRF. This adds the RK3368-specific logic necessary to reuse this driver. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Philipp Tomsich 提交于
As SPI support may be useful in the boot-flow, this adds support for configuring the SPI controller's clocks in the RK3368 clock driver. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
With the clock support in rk3368_clk_set_rate() conditionalized on various feature definitions, 'priv' can remain unused (e.g. in the SPL build when only MMC is enabled). Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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