This commit extends the sandbox to implement a dummy
extension_board_scan() function and enables the extension command in
the sandbox configuration. It then adds a test that checks the proper
functionality of the extension command by applying two Device Tree
overlays to the sandbox Device Tree.
Signed-off-by: NKory Maincent <kory.maincent@bootlin.com>
[trini: Limit to running on sandbox]
Signed-off-by: NTom Rini <trini@konsulko.com>

Add CPSW related nodes for AM642 SK. There are two CPSW ports on the
board but U-Boot supports only the first port.
Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>

AM64 as CPSW3G IP with 2 external ports. Add DT entries for the same
(based on kernel DT).

Disable second port as its by default set to ICSS usage on EVM.
Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>

Add R5 specific dts for AM64 SK
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NSinthu Raja <sinthu.raja@ti.com>

AM642 StarterKit (SK) board is a low cost, small form factor board
designed for TI’s AM642 SoC. It supports the following interfaces:
* 2 GB LPDDR4 RAM
* x2 Gigabit Ethernet interfaces capable of working in switch and MAC mode
* x1 USB 3.0 Type-A port
* x1 UHS-1 capable µSD card slot
* 2.4/5 GHz WLAN + Bluetooth 4.2 through WL1837
* 512 Mbit OSPI flash
* x2 UART through UART-USB bridge
* XDS110 for onboard JTAG debug using USB
* Temperature sensors, user push buttons and LEDs
* 40-pin Raspberry Pi compatible GPIO header
* 24-pin header for peripherals in MCU island (I2C, UART, SPI, IO)
* 54-pin header for Programmable Realtime Unit (PRU) IO pins
* Interface for remote automation. Includes:
	* power measurement and reset control
	* boot mode change

Add basic support for AM642 SK.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

Add I2C nodes for AM64 and enable pinmux for i2c0 for reading eeprom data.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

I2C EEPROM will be probed before SYSFW is available.
So drop the power-domains property for I2C.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

Chipid will be needed for SoC detection for all stages of U-Boot.
So make it u-boot,dm-spl
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

Enable support for selecting DTB within SPL based on EEPROM.
This will help to use single defconfig for both EVM and SK
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

I2C EEPROM data contains the board name and its revision.
Add support for:
- Reading EEPROM data and store a copy at end of SRAM
- Updating env variable with relevant board info
- Printing board info during boot.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

Add DDR VTT regulator.
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>

Add main domain GPIO nodes.
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>

In SPL, DDR should be made available by the end of board_init_f()
so that apis in board_init_r() can use ddr. Adding support for
triggering DDR initialization from board_init_f().
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>

Introduce ddr node for am642 needed for all ddr configurations.

Also, introduce the 1600MTs DDR4 configuration that is supported on the
am642-evm.
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>

Add initial support for dt that runs on r5.
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>

The AM642 EValuation Module (EVM) is a board that provides access to
various peripherals available on the AM642 SoC, such as PCIe, USB 2.0,
CPSW Ethernet, ADC, and more.

Add basic support.
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>

The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.

Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
  MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
  ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
  controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
  peripherals.
* Centralized System Controller for Security, Power, and Resource
  Management (DMSC).

See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2

Introduce basic support for the AM642 SoC to enable SD/MMC boot.
Introduce a limited set of MAIN domain peripherals under cbass_main and
a set of MCU domain peripherals under cbass_mcu.
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>

Add board specific initialization for am64x based boards.
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>

Change the memory attributes for the DDR regions used by the remote
processors on AM65x so that the cores can see and execute the proper code.

A separate table based on the previous K3 SoCs is introduced since the
number of remote processors and their DDR usage is different between the
SoC families.
Signed-off-by: NKeerthy <j-keerthy@ti.com>
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>

The AM642 SoCs use the Main R5FSS0 as a boot processor, and runs
the R5 SPL that performs the initialization of the System Controller
processor and starting the Arm Trusted Firmware (ATF) on the Arm
Cortex A53 cluster. The Core0 serves as this boot processor and is
parked in WFE after all the initialization. Core1 does not directly
participate in the boot flow, and is simply parked in a WFI.

Power down these R5 cores (and the associated RTI timer resources
that were indirectly powered up) after starting up ATF on A53 by
using the appropriate SYSFW API in release_resources_for_core_shutdown().
This allows these Main R5F cores to be further controlled from the
A53 to run regular applications.
Signed-off-by: NSuman Anna <s-anna@ti.com>
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>

To avoid any glitches on MMC clock line, make use of pm per and post
callbacks when loading sysfw.
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>

Use the System Firmware (SYSFW) loader framework to load and start
the SYSFW as part of the AM642 early initialization sequence. Also
make use of existing logic to detect if ROM has already loaded sysfw
and avoided attempting to reload and instead just prepare to use already
running firmware.

While at it also initialize the MAIN_UART1 pinmux as it is used by SYSFW
to print diagnostic messages.
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>

For AM642, ROM supports loading system firmware directly
from boot image. ROM passes information about the number of
images that are loaded to bootloader at a specific address
that is temporary.  Add support for storing this information
somewhere permanent before it gets corrupted.
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>

To access various control MMR functionality the registers need to
be unlocked. Do that for all control MMR regions in the MAIN domain.
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>

AM642 allows for booting from primary or backup boot media.
Both media can be chosen individually based on switch settings.
ROM looks for a valid image in primary boot media, if not found
then looks in backup boot media. In order to pass this boot media
information to boot loader, ROM stores a value at a particular
address. Add support for reading this information and determining
the boot media correctly.
Signed-off-by: NKeerthy <j-keerthy@ti.com>
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>

The AM642 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration to enable applications such as
Motor Drives, PLC, Remote IO and IoT Gateways.

Some highlights of this SoC are:
* Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F
  MCUs, and a single Cortex-M4F.
* Two Gigabit Industrial Communication Subsystems (ICSSG).
* Integrated Ethernet switch supporting up to a total of two external
  ports.
* PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory
  controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other
  peripherals.
* Centralized System Controller for Security, Power, and Resource
  Management (DMSC).

See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2Signed-off-by: NDave Gerlach <d-gerlach@ti.com>

This reverts commit d64b9cdc.

As pointed by [1] and [2], the reverted patch made every DT 'reg'
property translatable. What the patch was trying to fix was fixed in a
different way from previously submitted patches which instead of
correcting the generic address translation function fixed the issue with
appropriate platform code.

[1] https://patchwork.ozlabs.org/project/uboot/patch/1614324949-61314-1-git-send-email-bmeng.cn@gmail.com/
[2] https://lore.kernel.org/linux-clk/20210402192054.7934-1-dariobin@libero.it/T/Signed-off-by: NDario Binacchi <dariobin@libero.it>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

There are a number of platforms that depend on a SATA driver that has
been converted to require AHCI but the platforms themselves are behind
on other migrations that would make it trivial to enable AHCI.  Disable
SATA in these cases.
Signed-off-by: NTom Rini <trini@konsulko.com>

Clear feature disable CSR to turn on all features of hart. The detail
is specified at section, 'SiFive Feature Disable CSR', in user manual

https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdfSigned-off-by: NGreen Wan <green.wan@sifive.com>
Reviewed-by: NSean Anderson <seanga2@gmail.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NRick Chen <rick@andestech.com>

Add a callback harts_early_init() to start.S to allow different riscv
hart perform setup code for each hart as early as possible. Since all
the harts enter the callback, they must be able to run the same
setup.
Signed-off-by: NGreen Wan <green.wan@sifive.com>
Reviewed-by: NRick Chen <rick@andestech.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Check that a variable defined in /config/environment is found in the
run-time environment, and that clearing fdt_env_path from within that
node works.
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
[trini: Conditionalize the test being linked in]
Signed-off-by: NTom Rini <trini@konsulko.com>

This adds a test for the gpio-sysinfo driver.
Signed-off-by: NSean Anderson <sean.anderson@seco.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Supported peripherals: Ethernet, eMMC, Serial.

U-Boot SPL 2021.04-00911-g5fa1e2ff-dirty (Apr 23 2021 - 09:11:14
+0200)
Normal Boot
Trying to boot from MMC2

U-Boot 2021.04-00911-g5fa1e2ff-dirty (Apr 23 2021 - 09:11:14 +0200)

CPU:   Freescale i.MX8MQ rev2.1 at 1000 MHz
Reset cause: POR
Model: Ronetix iMX8M-CM SoM
DRAM:  1 GiB
WDT:   Started with servicing (60s timeout)
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... OK
In:    serial
Out:   serial
Err:   serial
Net:
Warning: ethernet@30be0000 (eth0) using random MAC address -
42:0d:e7:78:da:53
eth0: ethernet@30be0000
Hit any key to stop autoboot:  0
u-boot=>
Signed-off-by: NIlko Iliev <iliev@ronetix.at>

Console boot log:

U-Boot SPL 2021.04-00836-ga6232e06-dirty (Apr 16 2021 - 15:16:35 +0200)
Trying to boot from MMC1

U-Boot 2021.04-00836-ga6232e06-dirty (Apr 16 2021 - 15:16:35 +0200)

CPU:   Freescale i.MX7D rev1.3 1000 MHz (running at 792 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 44C
Reset cause: POR
Model: Ronetix iMX7-CM Board
Board: iMX7-CM
DRAM:  512 MiB
PMIC:  PFUZE3000 DEV_ID=0x30 REV_ID=0x11
MMC:   FSL_SDHC: 0, FSL_SDHC: 2
Loading Environment from MMC... OK
In:    serial
Out:   serial
Err:   serial
Net:
Warning: ethernet@30be0000 (eth0) using random MAC address - fe:be:37:01:5a:3f
eth0: ethernet@30be0000
Hit any key to stop autoboot:  0
Signed-off-by: NIlko Iliev <iliev@ronetix.at>

instead using ls and awk to determine file size use stat instead.
This fixes an invalid size reporting for user or group names that have
spaces in them.

This adds a dependency on the stat application which is part of
the coreutils package which also includes ls.
Signed-off-by: NTim Harvey <tharvey@gateworks.com>

Add initial support for Compulab iot-gate-imx8 board (imx8mm-cl-iot-gate).
The initial support includes:
 - MMC
 - eMMC
 - I2C
 - FEC
 - Serial console
Signed-off-by: NKirill Kapranov <kirill.kapranov@compulab.co.il>
Signed-off-by: NUri Mashiach <uri.mashiach@compulab.co.il>
Signed-off-by: NValentin Raevsky <valentin@compulab.co.il>
Signed-off-by: NYing-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Peter Robinson <pbrobinson@gmail.com>

Add board dts for imx8mm-cl-iot-gate
Signed-off-by: NKirill Kapranov <kirill.kapranov@compulab.co.il>
Signed-off-by: NUri Mashiach <uri.mashiach@compulab.co.il>
Signed-off-by: NValentin Raevsky <valentin@compulab.co.il>
Signed-off-by: NYing-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: Peter Robinson <pbrobinson@gmail.com>

Remove the invalid 'regulator-always-on' property to resolve:
starting USB...
Bus usb@2184000: Error enabling VBUS supply (ret=-13)
probe failed, error -13
Bus usb@2184200: USB EHCI 1.00
Signed-off-by: NTim Harvey <tharvey@gateworks.com>

Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier
board.

Genaral features:
- Ethernet 10/100
- Wifi/BT
- USB Type A/OTG
- Audio Out
- CAN
- LVDS panel connector

i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam.

i.Core MX8M Mini needs to mount on top of this Carrier board for
creating complete i.Core MX8M Mini C.TOUCH 2.0 board.

Linux dts commit details:

commit <a142252061ff> ("arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini
C.TOUCH 2.0")

Add support for it.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

Engicam EDIMM2.2 Starter Kit is an EDIMM 2.2 Form Factor Capacitive
Evaluation Board.

Genaral features:
- LCD 7" C.Touch
- microSD slot
- Ethernet 1Gb
- Wifi/BT
- 2x LVDS Full HD interfaces
- 3x USB 2.0
- 1x USB 3.0
- HDMI Out
- Mini PCIe
- MIPI CSI
- 2x CAN
- Audio Out

i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam.

i.Core MX8M Mini needs to mount on top of this Evaluation board for
creating complete i.Core MX8M Mini EDIMM2.2 Starter Kit.

Linux dts commit details:

commit <051c08eea682> ("arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini
EDIMM2.2 Starter Kit")

Add support for it.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>