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  1. 17 1月, 2010 2 次提交
  3. 08 1月, 2010 2 次提交
    • R
      mpc83xx: Add support for MPC8349 esd caddy2 · 1dee9be6
      由 Reinhard Arlt 提交于 
      The caddy2 is a variant of the already supported vme8349. So we just
add the differences to this board port. To better support those two
boards we switched from fixed SDRAM configuration to usage of
spd_sdram(). This is done by providing a board specific SPD EEPROM
routine with different values for both boards.
Signed-off-by: NReinhard Arlt <reinhard.arlt@esd.eu>
Signed-off-by: NStefan Roese <sr@denx.de>

changed to use mkconfig -t option instead, plus misc codingstyle fixes.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
      1dee9be6
    • A
      mpc83xx: Add NAND boot support for MPC8315E-RDB boards · 2e95004d
      由 Anton Vorontsov 提交于 
      The core support for NAND booting is there already, so this patch
is pretty straightforward.

There is one trick though: top level Makefile expects nand_spl to
be in nand_spl/board/$(BOARDDIR), but we can fully reuse the code
from mpc8313erdb boards, and so to not duplicate the code we just
symlink nand_spl/board/freescale/mpc8315erdb to mpc8313erdb.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>

o silence make during ln echo
o update documentation
o and avoid:

$ ./MAKEALL MPC8315ERDB_NAND
Configuring for MPC8315ERDB board...
sdram.o: In function `fixed_sdram':
/home/r1aaha/git/u-boot/nand_spl/board/freescale/mpc8313erdb/sdram.c:72: undefined reference to `udelay'

by renaming udelay -> __udelay in the spirit of commit
3eb90bad "Generic udelay() with watchdog
support".
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
      2e95004d
  5. 20 12月, 2009 1 次提交
    • T
      TWL4030 Add usb PHY support · bffbb2a8
      由 Tom Rix 提交于 
      The twl4030 provides a PHY device for connecting a link device,
like musb, to physical connection.

This change adds the twl4030 usb registers and functions for
initializing the PHY as required by omap3.
Signed-off-by: NTom Rix <Tom.Rix@windriver.com>
      bffbb2a8
  7. 18 12月, 2009 1 次提交
  9. 16 12月, 2009 1 次提交
  11. 08 12月, 2009 1 次提交
  13. 06 12月, 2009 1 次提交
  15. 28 11月, 2009 2 次提交
  17. 31 10月, 2009 1 次提交
  19. 28 10月, 2009 1 次提交
  21. 24 10月, 2009 1 次提交
    • T
      TI OMAP3 SDP3430: Initial Support · e63e5904
      由 Tom Rix 提交于 
      Start of support of
Texas Instruments Software Development Platform(SDP)
for OMAP3430 - SDP3430

Highlights of this platform are:
Flash Memory devices:
	Sibley NOR, Micron 8bit NAND and OneNAND
Connectivity:
	3 UARTs and expanded 4 UART ports + IrDA
	Ethernet, USB
Other peripherals:
	TWL5030 PMIC+Audio+Keypad
	VGA display
Expansion ports:
	Memory devices plugin boards (PISMO)
	Connectivity board for GPS,WLAN etc.
Completely configurable boot sequence and device mapping
etc.

Support default jumpering and:
 - UART1/ttyS0 console(legacy sdp3430 u-boot)
 - UART3/ttyS2 console (matching other boards,
		 and SDP HW docs)
 - Ethernet
 - mmc0
 - NOR boot

Currently the UART1 is enabled by default.  for
compatibility with other OMAP3 u-boot platforms,
enable the #define of CONSOLE_J9.

Conflicts:

	Makefile

Fixed the conflict with smdkc100_config by moving omap_sdp3430_config
to it is alphabetically sorted location above zoom1.
Signed-off-by: NDavid Brownell <david-b@pacbell.net>
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NTom Rix <Tom.Rix@windriver.com>
      e63e5904
  23. 19 10月, 2009 3 次提交
  25. 16 10月, 2009 2 次提交
  27. 14 10月, 2009 1 次提交
  29. 13 10月, 2009 3 次提交
  31. 30 9月, 2009 2 次提交
    • M
      On-chip ROM boot: MPC8536DS support · e40ac487
      由 Mingkai Hu 提交于 
      The MPC8536E is capable of booting from the on-chip ROM - boot from
eSDHC and boot from eSPI. When power on, the porcessor excutes the
ROM code to initialize the eSPI/eSDHC controller, and loads the mian
U-Boot image from the memory device that interfaced to the controller,
such as the SDCard or SPI EEPROM, to the target memory, e.g. SDRAM or
L2SRAM, then boot from it.

The memory device should contain a specific data structure with control
word and config word at the fixed address. The config word direct the
process how to config the memory device, and the control word direct
the processor where to find the image on the memory device, or where
copy the main image to. The user can use any method to store the data
structure to the memory device, only if store it on the assigned address.

The on-chip ROM code will map the whole 4GB address space by setting
entry0 in the TLB1, so the main image need to switch to Address space 1
to disable this mapping and map the address space again.

This patch implements loading the mian U-Boot image into L2SRAM, so
the image can configure the system memory by using SPD EEPROM.
Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      e40ac487
    • M
      NAND boot: MPC8536DS support · 9a1a0aed
      由 Mingkai Hu 提交于 
      MPC8536E can support booting from NAND flash which uses the
image u-boot-nand.bin. This image contains two parts: a 4K
NAND loader and a main U-Boot image. The former is appended
to the latter to produce u-boot-nand.bin. The 4K NAND loader
includes the corresponding nand_spl directory, along with the
code twisted by CONFIG_NAND_SPL. The main U-Boot image just
like a general U-Boot image except the parts that included by
CONFIG_SYS_RAMBOOT.

When power on, eLBC will automatically load from bank 0 the
4K NAND loader into the FCM buffer RAM where CPU can execute
the boot code directly. In the first stage, the NAND loader
copies itself to RAM or L2SRAM to free up the FCM buffer RAM,
then loads the main image from NAND flash to RAM or L2SRAM
and boot from it.

This patch implements the NAND loader to load the main image
into L2SRAM, so the main image can configure the RAM by using
SPD EEPROM. In the first stage, the NAND loader copies itself
to the second to last 4K address space, and uses the last 4K
address space as the initial RAM for stack.

Obviously, the size of L2SRAM shouldn't be less than the size
of the image used. If so, the workaround is to generate another
image that includes the code to configure the RAM by SPD and
load it to L2SRAM first, then relocate the main image to RAM
to boot up.
Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
      9a1a0aed
  33. 29 9月, 2009 1 次提交
  35. 26 9月, 2009 1 次提交
  37. 25 9月, 2009 6 次提交
  39. 14 9月, 2009 1 次提交
  41. 11 9月, 2009 3 次提交
  43. 05 9月, 2009 3 次提交