1. 26 2月, 2021 8 次提交
  2. 25 2月, 2021 28 次提交
  3. 23 2月, 2021 4 次提交
    • T
      Merge tag 'xilinx-for-v2021.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze · cbe607b9
      Tom Rini 提交于
      Xilinx changes for v2021.04-rc3
      
      qspi:
      - Support for dual/quad mode
      - Fix speed handling
      
      clk:
      - Add clock enable function for zynq/zynqmp/versal
      
      gem:
      - Enable clock for Versal
      - Fix error path
      - Fix mdio deregistration path
      
      fpga:
      - Fix buffer alignment for ZynqMP
      
      xilinx:
      - Fix reset reason clearing in ZynqMP
      - Show silicon version in SPL for Zynq/ZynqMP
      - Fix DTB selection for ZynqMP
      - Rename zc1275 to zcu1275 to match DT name
      cbe607b9
    • B
      spi: zynqmp_gqspi: fix set_speed bug on multiple runs · d9aa19ef
      Brandon Maier 提交于
      If zynqmp_qspi_set_speed() is called multiple times with the same speed,
      then on the second call it will skip recalculating the baud_rate_val as
      it assumes the speed is already configured correctly. But it will still
      write the baud_rate_val to the configuration register and call
      zynqmp_gqspi_set_tapdelay(). Because it skipped recalculating the
      baud_rate_val, it will use the initial value of 0 . This causes the
      driver to run at maximum speed which for many spi flashes is too fast and
      causes data corruption.
      
      Instead only write out a new baud_rate_val if we have calculated the
      correct baud_rate_val.
      
      This opens up another issue with the "if (speed == 0)", we don't save
      off the new plat->speed_hz value when setting the baud rate on the
      speed=0 path. Instead mimic what the Linux zynqmp gqspi driver does, and
      have speed==0 just use the same calculation as a normal speed. That will
      cause the baud_rate_val to use the slowest speed possible, which is the
      safest option.
      Signed-off-by: NBrandon Maier <brandon.maier@rockwellcollins.com>
      CC: jagan@amarulasolutions.com
      CC: michal.simek@xilinx.com
      CC: Ashok Reddy Soma <ashokred@xilinx.com>
      Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
      d9aa19ef
    • M
      arm64: zynqmp: Rename zc1275/zcu1275 to be aligned with DT name · 3600d47b
      Michal Simek 提交于
      Folder names corresponds to DT name. These boards have been renamed from
      zc1275 to zcu1275 by commit shown below and this should be the part of that
      commit.
      
      Fixes: 420d4467 ("arm64: zynqmp: Rename zc1275 to zcu1275")
      Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
      3600d47b
    • M
      net: gem: Fix error path in zynq_gem_probe · a13a8218
      Michal Simek 提交于
      Clean up error path in connection where priv->rxbuffers and priv->tx_bd are
      allocated.
      Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
      a13a8218