- 31 10月, 2016 3 次提交
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由 Simon Glass 提交于
This function is called from outside the driver. It should be placed into common SoC code. Move it. Also rename the driver symbol to be more consistent with the other rockchip clock drivers. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
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由 Jacob Chen 提交于
clk_rk3399 is driver name, not device name Signed-off-by: NJacob Chen <jacob2.chen@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Sandy Patterson 提交于
I am not sure why this limit is changing. But my kernel doesn't load when it's above 256. This was testing on the rock2 board. Signed-off-by: NSandy Patterson <apatterson@sightlogix.com> Updated commit subject: Signed-off-by: NSimon Glass <sjg@chromium.org>
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- 30 10月, 2016 23 次提交
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由 Chen-Yu Tsai 提交于
The Cubieboard4 is an A80 SoC based development board from Cubietech. This board has a UART port, 4 USB host ports, a USB 3.0 OTG connector, HDMI and VGA outputs, a micro SD slot, 8G eMMC flash, 2G DRAM, a WiFi/BT combo chip, headphone and microphone jacks, IR receiver, and GPIO headers. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Stefan Brüns 提交于
mksunxiboot is useful outside of u-boot, it is e.g. used by sunxi-tools. Signed-off-by: NStefan Brüns <stefan.bruens@rwth-aachen.de> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Chen-Yu Tsai 提交于
The A80 Optimus Board was launched with the Allwinner A80 SoC. It was jointly developed by Allwinner and Merrii. This board has a UART port, a JTAG connector, 2 USB host ports, a USB 3.0 OTG connector, an HDMI output, a micro SD slot, 16G eMMC flash, 2G DRAM, a camera sensor interface, a WiFi/BT combo chip, a headphone jack, IR receiver, and additional GPIO headers. Signed-off-by: NChen-Yu Tsai <wens@csie.org> [hdegoede@redhat.com: update existing Merrii_A80_Optimus_defconfig instead of adding a new defconfig] Acked-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Amit Singh Tomar 提交于
Mostly by adding MACH_SUN50I to some existing #ifdefs enable support for the the HCI0 USB host controller on the A64. Fix up some minor 64-bit hiccups on the way. Add the bare minimum DT bits to the A64 .dtsi and enable the controllers and the PHY on the Pine64. This is limited to the first USB controller at the moment, which is connected to the lower USB socket on the Pine64 board. [Andre: remove unneeded defines, enable OHCI, add commit message] Signed-off-by: NAmit Singh Tomar <amittomer25@gmail.com> Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Reviewed-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Chen-Yu Tsai 提交于
Both the A80 Optimus board and the Cubieboard 4 use a zq value of 4145117, or 0x3f3fdd. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Stefan Mavrodiev 提交于
Originally dram clock was set to 480MHz, but this behaves unstable. To improve stability the clock is reduced to 384MHz Signed-off-by: NStefan Mavrodiev <stefan.mavrodiev@gmail.com> Reviewed-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Chen-Yu Tsai 提交于
The A80 has SID e-fuses. Like other newer SoCs, the actual e-fuses are at an offset of 0x200 within the SID address space. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Andre Przywara 提交于
The sun8i-emac driver works fine with the A64 Ethernet IP, but we are missing an alias entry to trigger the driver instantiation by U-Boot. Add the line to point U-Boot to the Ethernet DT node. This enables TFTP boot on the Pine64. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Reviewed-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Chen-Yu Tsai 提交于
In Allwinner's SDK the A80 is clocked to 1008 MHz by default. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Masahiro Yamada 提交于
ARCH_SUNXI selects DM_USB, where CONFIG_USB_MAX_CONTROLLER_COUNT is not used. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Philipp Tomsich 提交于
The A80 can support 8-bit eMMC with reset on the PC pingroups. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Jagan Teki 提交于
CONFIG_SUNXI -> CONFIG_ARCH_SUNXI and removed CONFIG_SUNIX from config_whitelist.txt Cc: Simon Glass <sjg@chromium.org> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Hans de Goede <hdegoede@redhat.com> Signed-off-by: NJagan Teki <jteki@openedev.com> Reviewed-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Philipp Tomsich 提交于
Now that DRAM initialization and clock setup is supported, we can enable SPL for the A80. [wens@csie.org: Added commit message] Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Philipp Tomsich 提交于
This is a cleaned up version set_pll() from Allwinner's boot0 source (bootloader/basic_loader/bsp/bsp_for_a80/common/common.c). [wens@csie.org: Added commit message; style cleanup] Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Philipp Tomsich 提交于
Since the A80 has many cores which we intend to use in SMP fashion, we should set the SMP bit for the boot CPU. [wens@csie.org: Added commit message] Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Philipp Tomsich 提交于
On sun9i, the GTBUS manages transaction priority and bandwidth for multiple read ports when accessing DRAM. The initialisation mirrors the settings from Allwinner's boot0 for now, even though this may not be optimal for all applications (e.g. headless systems might want to give priority to IO modules). Adding a common callout to gtbus_init() from the SPL clock init with a weakly defined implementation in sunxi/clock.c to fallback to for platforms that don't require this. [wens@csie.org: Moved gtbus_sun9i.c to arch/arm/mach-sunxi/; style cleanup] Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Philipp Tomsich 提交于
This adds DRAM initialisation code for sun9i, which calculates the appropriate timings based on timing information for the supplied DDR3 bin and the clock speeds used. With this DRAM setup, we have verified DDR3 clocks of up to 792MHz (i.e. DDR3-1600) on the A80-Q7 using a dual-channel configuration. [wens@csie.org: Moved dram_sun9i.c to arch/arm/mach-sunxi/; style cleanup] Signed-off-by: NChen-Yu Tsai <wens@csie.org> [hdegoede@redhat.com: Drop some huge non-documenting #if 0 ... #endif blocks] [hdegoede@redhat.com: Fix checkpatch warnings] Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Andre Przywara 提交于
OHCI has a known limitation of allowing only 32-bit DMA buffer addresses, so we have a lot of u32 variables around, which are assigned to pointers and vice versa. This obviously creates issues with 64-bit systems, so the compiler complains here and there. To allow compilation for 64-bit boards which use only memory below 4GB anyway (and to avoid more invasive fixes), adjust some casts and types and assume that the EDs and TDs are all located in the lower 4GB. This fixes compilation of the OHCI driver for the Pine64. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Reviewed-by: NHans de Goede <hdegoede@redhat.com>
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- 29 10月, 2016 14 次提交
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由 Tom Rini 提交于
This was turned off by accident, re-enble. Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Jagan Teki 提交于
Signed-off-by: NJagan Teki <jagan@openedev.com>
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由 Stephen Warren 提交于
ARMv7 Tegra boards aren't currently covered by any other travis-ci jobs. Add a new job to build them. Signed-off-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NHeiko Schocher <hs@denx.de>
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由 Stephen Warren 提交于
Use buildman to compile any U-Boot binary tested by test/py. This re-uses all the work done elsewhere to make buildman work within Travis-CI, in particular related to toolchain downloading and buildman config file creation. Signed-off-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NHeiko Schocher <hs@denx.de>
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由 Masahiro Yamada 提交于
Introduce run-time DDR PHY training. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
Add the LD11 SoC data and adjuts the printf() format because this is a 64-bit SoC. Otherwise, 16-digits pointer addresses would break the log format. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
Do not hard-code the number of DX blocks because it is a different value for LD11 SoC. Move the macro NR_DATX8_PER_DDRPHY to ddrphy-training.c since it is the last user. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
The DDR PHY register view of LD11 is slightly different from that of LD4/Pro4/sLD8, but it will be possible to share the register macros (and I want to re-use as much code as possible). Change the code in the more flexible form. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
The USB boot without the stand-by MPU is available on ES3 or later of LD11 SoC, but the code in this if-conditional block must not be run when booting from USB. Check if the boot device is USB, and skip the code in the case. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
At the moment, the clk driver is not clever enough to automatically enable parent clocks like Linux. Enable the STDMAC clock explicitly if USB is enabled. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
The status register should be polled. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
This PHY might be used for other SoCs in the future. Avoid including the SoC name in the header name. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
- Constify UMC setting data arrays - Merge data arrays *_d0 and *_d1. - Add PHY parameters for LD20 C1 board Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
After SoC evaluation, they turned out unnecessary. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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