Building u-boot tools with clang as a host compiler e.g. on
FreeBSD with `gmake HOSTCC=clang CONFIG_USE_PRIVATE_LIBGCC=y tools`
leads to many warnings [1] for every compiler invocation since
commit 598e2d33. Part of mentioned commit imports linux patches:

 - kbuild: LLVMLinux: Adapt warnings for compilation with clang
 - kbuild: LLVMLinux: Add Kbuild support for building kernel with Clang

No version of clang supports the gcc fno-delete-null-pointer-checks
though, but it is only passed to clang. Gcc does not have the clang
specific Qunused-arguments for the target. Furthermore several
warnings are disabled which aren't encountered in u-boot. Since such
a build has worked for quite some time and works after removing these
changes, just remove the clang specific handling to restore normal
building with clang as hostcc.

[1] Actual warnings
-------------------
  GEN     include/autoconf.mk.dep
arm-freebsd-gcc: unrecognized option '-Qunused-arguments'

  HOSTCC  scripts/basic/fixdep
clang: warning: argument unused during compilation:
                '-fno-delete-null-pointer-checks'

cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl>

Patch (SHA1: bd694244)
dfu: Introduction of the "dfu_hash_algo" env variable for checksum method
setting

already introduced more generic handling of the crc32 calculation.
Up till now the CRC32 of received data was calculated unconditionally.
This patch changes this and from now - by default the crc32 is NOT
calculated anymore.
Signed-off-by: NLukasz Majewski <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>

Sometimes, a zero-length packet is required at the end of an IN
transaction so that the host knows the device is done sending data.
Enhance ci_udc to send a zlp when necessary. See the comments for
more details.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

usb_gadget_unregister_driver() is called to tear down the USB device mode
stack. Fix the driver to stop the USB HW (which causes any attached host
to notice the disappearance of the device), and free all allocations
(which obviously prevents memory leaks).
Signed-off-by: NStephen Warren <swarren@nvidia.com>

If allocation of the ep0 req fails, clean up all the allocations that
were made in ci_udc_probe().
Signed-off-by: NStephen Warren <swarren@nvidia.com>

ci_ep_alloc_request() avoids allocating multiple request objects for ep0
by keeping a record of the first req allocated for ep0, and always
returning that instead of allocating a new req. However, if this req is
ever freed, the record of the previous allocation is not cleared, so
ci_ep_alloc_request() will keep returning this stale pointer. Fix
ci_ep_free_request() to clear the record of the previous allocation.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

ci_pullup()'s !is_on path contains a cut/paste copy of udc_disconnect().
Remove the duplication by simply calling udc_disconnect() instead.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Signed-off-by: NTom Rini <trini@ti.com>

'r' of rESR_RTLF is a mistake of E.
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

This fixes checkpatch's warning.
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

The R7S72100 of ARM SoC that Renesas manufactured has one Ether port.
This has the same IP SH-Ether. This patch adds support of the R7S72100
in SH-Ether.
Signed-off-by: NNobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>

Currently, flash quad bit is set in "spi_flash_validate_params" and later
at the end in the same api, we write 0 to status register for few flashes,
thereby overriding the quad bit set. This fix moves the quad bit setting
outside this api in "spi_flash_probe_slave"
Signed-off-by: NSourav Poddar <sourav.poddar@ti.com>
Reviewed-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>

This mirrors the conventions used in other SPI drivers (kirkwood,
davinci, atmel, et al) where the din/dout buffer can be NULL when the
received/transmitted data isn't important.  This reduces the need for
allocating additional buffers when write-only/read-only functionality is
needed.

In the din == NULL case, the received data is simply not stored.  In the
dout == NULL case, zeroes are transmitted.
Signed-off-by: NAndrew Ruder <andrew.ruder@elecsyscorp.com>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Reviewed-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>

Added support for Spansion chip "S25FL512S_512K".
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>

This family is supported by the TPS65218 PMIC.  Implement a scale_vcores
to set the MPU and CORE voltage correctly to the max frequency that is
supported (and what we will be scaling them to in setup_dplls()).
Signed-off-by: NTom Rini <trini@ti.com>

Add a driver for the TPS65218 PMIC which is used by TI AM43xx SoCs and
may be used by TI AM335x SoCs.
Signed-off-by: NTom Rini <trini@ti.com>

Similar to OMAP4/5 we need to scale the voltage up prior to changing the
clock frequencies up higher.  Add a similar hook to start with.
Signed-off-by: NTom Rini <trini@ti.com>

Signed-off-by: NTom Rini <trini@ti.com>

Cc: trini@ti.com
Signed-off-by: NHannes Petermaier <oe5hpm@oevsv.at>

in almost all cases we need the i2c commands within the u-boot shell.
So we enable them within the common section.

Cc: trini@ti.com
Signed-off-by: NHannes Petermaier <oe5hpm@oevsv.at>

if we have no NAND-Chip, we don't need the gpmc-controller and therefore
is no need to init it.

Cc: trini@ti.com
Signed-off-by: NHannes Petermaier <oe5hpm@oevsv.at>

Cc: trini@ti.com
Signed-off-by: NHannes Petermaier <oe5hpm@oevsv.at>

Signed-off-by: NHannes Petermaier <oe5hpm@oevsv.at>

For usage of timer6 within B&R we need this defines to enable clock
modules and clk-source.

Also the 'Timer register bits' are expanded.

By the way we add defines for all timers within AM335x SoC.

Cc: trini@ti.com
Signed-off-by: NHannes Petermaier <oe5hpm@oevsv.at>

After enabling a module, SW has to wait on IDLEST bit
until it is Fully functional. This wait is missing for UART module
and there is a immediate access of UART registers after this. So there
is a chance of hang on this module( This can happen when we are running
from MPU SRAM). So waiting for IDLEST bit.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

loadbootenv expects devtype variable to be set. This is missing in
mmcboot command. With this the following error comes:
U-Boot# run mmcboot
mmc0 is current device
SD/MMC found on device 0
** Bad device usb 0 **
** Bad device usb 0 **
Fixing this by setting devtype as mmc.
Reported-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

commit a0a37183 "ARM: omap: merge GPMC initialization code for
all platform" needs CONFIG_NOR, CONFIG_NAND or CONFIG_CMD_ONENAND
to be set to access flash. Add CONFIG_NAND for tam3517 derived
boards to prevent the following error: "nand: error: Unable to
find NAND settings in GPMC Configuration - quitting"

cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl>

Enable support of nand ecclayout command.
Acked-By: NMurali Karicheri <m-karicheri2@ti.com>
Acked-by: NVitaly Andrianov <vitalya@ti.com>
Signed-off-by: NWingMan Kwok <w-kwok2@ti.com>
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>

Currently PWREMU_MGMT is not configured in the Linux generic UART
driver as this register seems to be specific TI UART IP. So this
needs to be enabled in u-boot to use UART1 from kernel space.
Acked-By: NVitaly Andrianov <vitalya@ti.com>
Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com>
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>

With the changes to the i2c framework (and adopting the omap24xx_i2c
driver to them) we can no longer call i2c functions prior to gd having
been set and cleared.  When SPL booting, this is handled by setting gd
to point to SRAM in s_init.  However in the cases where we are loaded
directly by ROM (memory mapped NOR or QSPI) we need to make use of the
normal hooks to slightly delay these calls.
Signed-off-by: NTom Rini <trini@ti.com>

We have two contexts for booting these platforms.  One is SPL which is
roughly: reset, cpu_init_crit, lowlevel_init, s_init, sdram_init, _main,
board_init_f from SPL, ... then U-Boot loads.  The other is a
memory-mapped XIP case (NOR or QSPI) where we do not run an SPL.  In
this case we go, roughly: reset, cpu_init_crit, lowlevel_init, s_init,
_main, regular board_init_f.

In the first case s_init will set a valid gd and then be able to call
sdram_init which in many cases will need i2c (which needs a valid gd for
gd->cur_i2c_bus).  In this second case we must (and are able to and
should) defer sdram_init() into dram_init() called by board_init_f as gd
will have been set in _main and cleared in board_init_f.
Signed-off-by: NTom Rini <trini@ti.com>

The patch populates the slave data which will be used by flash driver to
set the  flash quad enable bit.
Signed-off-by: NSourav Poddar <sourav.poddar@ti.com>

The ePOS EVM and EVM SK have QSPI as an option to boot.  Add a qspiboot
target that utilizes QSPI for env and so forth as an example of best
practices.  As QSPI is booted from directly we need to chang
CONFIG_SYS_TEXT_BASE.

Note that on ePOS EVM the QSPI and NAND are mutually exclusive choices
we need to handle that elsewhere, once NAND support is also added.
Signed-off-by: NSourav Poddar <sourav.poddar@ti.com>
Signed-off-by: NTom Rini <trini@ti.com>

updates documentation with explanation on how to select ECC schemes.
Signed-off-by: NPekon Gupta <pekon@ti.com>

This patch add support for BCH16_ECC to omap_gpmc driver.

*need to BCH16 ECC scheme*
With newer SLC Flash technologies and MLC NAND, and large densities, pagesizes
Flash devices have become more suspectible to bit-flips. Thus stronger
ECC schemes are required for protecting the data.
But stronger ECC schemes have come with larger-sized ECC syndromes which require
more space in OOB/Spare. This puts constrains like;
(a) BCH16_ECC can correct 16 bit-flips per 512Bytes of data.
(b) BCH16_ECC generates 26-bytes of ECC syndrome / 512B.
Due to (b) this scheme can only be used with NAND devices which have enough
OOB to satisfy following equation:
OOBsize per page >= 26 * (page-size / 512)
Signed-off-by: NPekon Gupta <pekon@ti.com>

GPMC can support simultaneous processing of 8 512Byte data chunks, in parallel
Signed-off-by: NPekon Gupta <pekon@ti.com>