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  1. 25 5月, 2021 17 次提交
  3. 20 5月, 2021 1 次提交
    • S
      arm: mvebu: armada-3720-uDPU.dts: Change back to phy-mode "2500base-x" · c3506013
      由 Stefan Roese 提交于 
      With commit 8678776d (arm: mvebu: armada-3720-uDPU: fix PHY mode
definition to sgmii-2500) the PHY mode was switch to "sgmii-2500", even
when this is functionally incorrect since "2500base-x" was not supported
in U-Boot at that time. As this mode is now supported (at least present
in the headers), this patch moves back to the orinal version.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Jakov Petrina <jakov.petrina@sartura.hr>
Cc: Vladimir Vid <vladimir.vid@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
      c3506013
  5. 19 5月, 2021 15 次提交
  7. 17 5月, 2021 4 次提交
    • B
      riscv: Group assembly optimized implementation of memory routines into a submenu · 89419279
      由 Bin Meng 提交于 
      Currently all assembly optimized implementation of memory routines
show up at the top level of the RISC-V architecture Kconfig menu.
Let's group them together into a submenu.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
      89419279
    • B
      riscv: Fix memmove and optimise memcpy when misalign · 703b84ec
      由 Bin Meng 提交于 
      At present U-Boot SPL fails to boot on SiFive Unleashed board, due
to a load address misaligned exception happens when loading the FIT
image in spl_load_simple_fit(). The exception happens in memmove()
which is called by fdt_splice_().

Commit 8f0dc4cf introduces an assembly version of memmove but
it does take misalignment into account (it checks if length is a
multiple of machine word size but pointers need also be aligned).
As a result it will generate misaligned load/store for the majority
of cases and causes significant performance regression on hardware
that traps misaligned load/store and emulate them using firmware.

The current behaviour of memcpy is that it checks if both src and
dest pointers are co-aligned (aka congruent modular SZ_REG). If
aligned, it will copy data word-by-word after first aligning
pointers to word boundary. If src and dst are not co-aligned,
however, byte-wise copy will be performed.

This patch was taken from the Linux kernel patch [1], which has not
been applied at the time being. It fixes the memmove and optimises
memcpy for misaligned cases. It will first align destination pointer
to word-boundary regardless whether src and dest are co-aligned or
not. If they indeed are, then wordwise copy is performed. If they
are not co-aligned, then it will load two adjacent words from src
and use shifts to assemble a full machine word. Some additional
assembly level micro-optimisation is also performed to ensure more
instructions can be compressed (e.g. prefer a0 to t6).

With this patch, U-Boot boots again on SiFive Unleashed board.

[1] https://patchwork.kernel.org/project/linux-riscv/patch/20210216225555.4976-1-gary@garyguo.net/

Fixes: 8f0dc4cf ("riscv: assembler versions of memcpy, memmove, memset")
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
      703b84ec
    • S
      riscv: Fix arch_fixup_fdt always failing without /chosen · e90cb0db
      由 Sean Anderson 提交于 
      If /chosen was missing, chosen_offset would never get updated with the new
/chosen node. This would cause fdt_setprop_u32 to fail. This patch fixes
this by setting chosen_offset. In addition, log any errors from setting
boot-hartid as well.

Fixes: 5370478d ("riscv: Add boot hartid to device tree")
Signed-off-by: NSean Anderson <seanga2@gmail.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NRick Chen <rick@andestech.com>
Reviewed-by: NAtish Patra <atish.patra@wdc.com>
      e90cb0db
    • B
      riscv: Split SiFive CLINT support between SPL and U-Boot proper · a6d7e8c9
      由 Bin Meng 提交于 
      At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to
control the enabling of SiFive CLINT support in both SPL (M-mode)
and U-Boot proper (S-mode). So for a typical SPL config that the
SiFive CLINT driver is enabled in both SPL and U-Boot proper, that
means the S-mode U-Boot tries to access the memory-mapped CLINT
registers directly, instead of the normal 'rdtime' instruction.

This was not a problem before, as the hardware does not forbid the
access from S-mode. However this becomes an issue now with OpenSBI
commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain")
that the SiFive CLINT register space is protected by PMP for M-mode
access only. U-Boot proper does not boot any more with the latest
OpenSBI, that access exceptions are fired forever from U-Boot when
trying to read the timer value via the SiFive CLINT driver in U-Boot.

To solve this, we need to split current SiFive CLINT support between
SPL and U-Boot proper, using 2 separate Kconfig options.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSean Anderson <seanga2@gmail.com>
      a6d7e8c9
  9. 16 5月, 2021 3 次提交