The basic blocks of the A23 are similar to the A31 (sun6i). Re-use
sun6i code for initial clock, gpio, and uart setup.

There is no SPL support for A23, as we do not have any documentation
or sample code for DRAM initialization.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

The Allwinner A23 SoC has reset controls like the A31 (sun6i).
The FIFO address is also the same as sun6i.

Re-use code added for sun6i.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

Allwinner SoCs provide uart0 muxed with mmc0, which can then be used
with a micro SD breakout board. On the A23, this is the only way to
use uart0.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

UART0 pin muxes on the A23 have a different function value.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

The watchdog on sun6i/sun8i has a different layout.

Add the new layout and fix up the setup functions so that reset works.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NIan Campbell <ijc@hellion.org.uk>
[ ijc -- removed sun5i workaround from sun6i/sun8i codepath as discussed ]

The RTC hardware has been moved out of the timer block on sun6i/sun8i.
In addition, there are more watchdogs available.

Also note that the timer block definition is not completely accurate
for sun5i/sun7i. Various blocks are missing or have been moved out.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

On later Allwinner SoCs, the watchdog hardware is by all means a
separate hardware block, with its own address range and interrupt
line.

Move the register definitions to a separate file to facilitate
supporting newer SoCs.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

BOOT_TARGET_DEVICES includes MMC unconditionally. This breaks when
CONFIG_CMD_MMC is not defined. Use a secondary macro to conditionally
include it when CONFIG_MMC is enabled, as we do for CONFIG_AHCI.

This is used when we want to use uart0 from port F, which conflicts
with mmc0.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

Many people are still using old linux-sunxi-3.4 kernels on sunxi devices,
adding the proper MACH_TYPE defines for this allows people to switch to
upstream u-boot, so that we can stop maintaining the linux-sunxi u-boot fork.

These machine-ids are all properly registered at:

http://www.arm.linux.org.uk/developer/machines/Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

Unify the sunxi Kconfig code, instead of having separate code blocks for
each of sun4i - sun7i.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

Enable the second sdcard slot found on some boards. Note that we do not
set CONFIG_MMC_SUNXI_SLOT_EXTRA for the SPL, as having it there is not useful,

Except for on the Mele-M3 where the second sdcard is an eMMC, from which the
device can also boot, and there we want to have both in the SPL, so that
a single u-boot binary can both from both. So for the M3 we do prefix the
defconfig setting with the special "+S:" syntax so that it applies to the
SPL too.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

None of the known sunxi devices actually use mmc1 routed through PH, where
as some devices do actually use mmc1 routed through PG, so change the routing
of mmc1 to PG. If in the future we encounter devices with mmc1 routed through
PH, we will need to change things to be a bit more flexible.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

sunxi SOCs can boot from both mmc0 and mmc2, detect from which one we're
booting, and make that one "mmc dev 0" so that a single u-boot binary can
be used for both the onboard eMMC and for external sdcards.

When we're booting from mmc2, we make it dev 0 because that is where the SPL
will load the tertiary payload (the actual u-boot binary in our case) from,
see: common/spl/spl_mmc.c, which has dev 0 hardcoded everywhere.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

Note we also drop the SPL check for initializing the 2nd mmc slot, the SPL
check is not necessary with Kconfig, because only options explicitly marked
as also being for the SPL get set during SPL builds.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

The Colombus board is an A31 evaluation board from WITS Technology.

Maxime has kindly agreed to maintain this board.

[1] http://lists.denx.de/pipermail/u-boot/2014-September/190043.htmlSigned-off-by: NChen-Yu Tsai <wens@csie.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

Add a new sun6i machine that supports UART and MMC.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
[wens@csie.org: use SPDX labels, adapt to Kconfig system, drop ifdef
		around mmc and smp code, drop MACH_TYPE]
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
[wens@csie.org: commit message was "ARM: sunxi: Setup the A31 UART0 muxing"]
[wens@csie.org: reorder #ifs by SUN?I]
[wens@csie.org: replace magic numbers with GPIO definitions]
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

UART0 is the default debug/console UART on the A31.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

The mmc hardware on sun6i has an extra reset control that needs to
be de-asserted prior to usage. Also the FIFO address is different.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
[wens@csie.org: use setbits_le32 for reset control, drop obsolete changes,
		rewrite different FIFO address handling, add commit message]
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

This patch adds the basic clocks support for the Allwinner A31 (sun6i)
processor. This code will not been compiled until the build is hooked
up in a later patch. It has been split out to keep the patches manageable.

This includes changes from the following commits from u-boot-sunxi:

a92051b ARM: sunxi: Add sun6i clock controller structure
1f72c6f ARM: sun6i: Setup the UART0 clocks
5f2e712 ARM: sunxi: Enable pll6 by default on all models
2be2f2a ARM: sunxi-mmc: Add mmc support for sun6i / A31
12e1633 ARM: sun6i: Add initial clock setup for SPL
1a9c9c6 ARM: sunxi: Split clock code into common, sun4i and sun6i code
0b194ee ARM: sun6i: Properly setup the PLL LDO in clock_init_safe
b54c626 sunxi: avoid sr32 for APB1 clock setup.
68fe29c sunxi: remove magic numbers from clock_get_pll{5,6}
c89867d sunxi: clocks: clock_get_pll5 prototype and coding style
501ab1e ARM: sunxi: Fix sun6i PLL6 settings
37f669b ARM: sunxi: Fix macro names for mmc and uart reset offsets
61de1e6 ARM: sunxi: Correct comment for MBUS1 register in sun6i clock definitions
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NIan Campbell <ijc@hellion.org.uk>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
[wens@csie.org: styling fixes reported by checkpatch.pl]
[wens@csie.org: drop unsupported SPL code block and unused gpio.h header]
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Cc: Tom Cubie <Mr.hipboi@gmail.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

The A31 has a new module called PRCM, or Power, Reset Control Module.
This module controls clocks and resets for RTC block modules, and also
PLL biasing in the main clock module.

This patch adds the register definitions, and also enables the clocks
and resets for the RTC block PIO (pin controller) and P2WI (push-pull
2 wire interface) which is used to talk to the PMIC.
Signed-off-by: NOliver Schinagl <oliver@schinagl.nl>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
[wens@csie.org: spacing fixes reported by checkpatch.pl]
[wens@csie.org: Use setbits helper in PRCM init function]
[wens@csie.org: rephrase commit message to explain what the hardware
		supports and what we actually enable]
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

A31 has several new and changed memory address. This patch adds them.
Signed-off-by: NOliver Schinagl <oliver@schinagl.nl>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

BOOT_TARGET_DEVICES includes USB unconditionally. This breaks when
CONFIG_CMD_USB is not defined. Use a secondary macro to conditionally
include it when CONFIG_EHCI is enabled, as we do for CONFIG_AHCI.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

We have already defined macros for pull-up/down values in the
GPIO header. Use them instead of magic numbers when configuring
the UART pins.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

The Mele M3 is yet another Allwinnner based Android top set box from Mele.

It uses a housing similar to the A2000, but without the USM sata storage slot
at the top.

It features an A20 SoC, 1G RAM, 4G eMMC (unique for Allwinner devices),
100Mbit ethernet, HDMI out, 3 USB A receptacles, VGA, and A/V OUT connections.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

Allwinner A20/A23/A31's SD/MMC host support SDHC High Capacity feature.
Signed-off-by: NWills Wang <wills.wang.open@gmail.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

This adds support for the Olimex A20-OLinuXino-Lime2
https://www.olimex.com/Products/OLinuXino/A20/A20-OLinuXIno-LIME2

Differences to previous Lime boards are 1GB RAM and gigabit ethernet
Signed-off-by: NIain Paton <ipaton0@gmail.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

Since the environment "VENDOR" is set in tcsh, it must be cleared in our
makefile.  Otherwise, boards without CONFIG_SYS_VENDOR fail to build:

  > make CROSS_COMPILE=arm-linux-gnueabi- wandboard_quad_defconfig all
    [ snip ]
    AR      arch/arm/lib/lib.a
    CC      arch/arm/lib/eabi_compat.o
  scripts/Makefile.build:55: /home/foo/u-boot/board/unknown/wandboard/ \
  Makefile: No such file or directory
  make[2]: *** No rule to make target `/home/foo/u-boot/board/unknown/ \
  wandboard/Makefile'.  Stop.
  make[1]: *** [board/unknown/wandboard] Error 2
  make: *** [__build_one_by_one] Error 2
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Reported-by: NTom Everett <tom@khubla.com>
Reported-by: NJeroen Hofstee <jeroen@myspectrum.nl>

Without the private libgcc, we need a full multilib toolchain with
different libgcc or multiple toolchains to build all BE/LE and
hard-float/soft-float variants of MIPS boards.  That is not feasible.

This commit allows us to build all the MIPS boards with a single
kernel.org toolchain:

https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/
x86_64-gcc-4.9.0-nolibc_mips-linux.tar.xz

This change sounds reasonable for most users.  If necessary,
you can disable this option via "make menuconfig" or friends.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>

When spl/.config is updated by "make spl/menuconfig" or friends,
spl/include/config/auto.conf, spl/include/generated/autoconf.h
and some other files must be updated by "make silentoldconfig".

There is no hook for SPL in the top Makefile, so this commit
touches .config when spl/.config is updated to invoke silentoldconfig.
Likewise for TPL.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

cmd_u-boot-spl includes $(PLATFORM_LIBS) which changes
when CONFIG_USE_PRIVATE_GCC is updated.  The u-boot-spl image
should be re-linked if any prerequisite is newer than it
or the command line has changed.
$(call, if_changed,...) should be used instead of $(call cmd,...).
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

The private libgcc is supported only on ARM, MIPS, PowerPC, SH, x86.
Those architectures should "select" HAVE_PRIVATE_LIBGCC and
CONFIG_USE_PRIVATE_LIBGCC should depend on it.

Currently, this option is enabled on Tegra boards and x86 architecture.
Move the definition from header files to Kconfig.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Tested-by: NSimon Glass <sjg@chromium.org>
Acked-by: NSimon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Tom Warren <twarren@nvidia.com>

Now CONFIG_USE_PRIVATE_LIBGCC is only used as a boolean macro.
Remove CONFIG_USE_PRIVATE_LIBGCC=path/to/libgcc syntax.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Tested-by: NSimon Glass <sjg@chromium.org>
Acked-by: NSimon Glass <sjg@chromium.org>

The motivation of this commit is to change CONFIG_USE_PRIVATE_LIBGCC
to a boolean macro so we can move it to Kconfig.

In the current implementation, there are two forms of syntax
for this macro:

  - CONFIG_USE_PRIVATE_LIBGCC=y
  - CONFIG_USE_PRIVATE_LIBGCC=path/to/private/libgcc

The latter is only used by x86 architecture.
With a little bit refactoring, it can be converted to the former.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Tested-by: NSimon Glass <sjg@chromium.org>
Acked-by: NSimon Glass <sjg@chromium.org>

CONFIG_SYS_HZ is always defined as 1000 in config_fallbacks.h
(but some boards still have redundant definitions).

This commit moves the definition and the document in README to
Kconfig.  Since lib/Kconfig can assure that CONFIG_SYS_HZ is 1000,
the sanity check in lib/time.c should be removed.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: NMarek Vasut <marex@denx.de>

Add target to build it automatically upon "make" / MAKEALL. This can/should
be set by board / cpu specific headers if a special U-Boot image is
required for this SoC / board.

E.g. used by Marvell Armada XP to automatically build the u-boot.kwb
target.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>

This patch integrates the Barebox version of this kwbimage.c file into
U-Boot. As this version supports the image version 1 type for the
Armada XP / 370 SoCs.

It was easier to integrate the existing and known to be working Barebox
source than to update the current U-Boot version to support this
v1 image header format. Now all Marvell MVEBU SoCs are supported:

Image type 0: Kirkwood & Dove
Image type 1: Armada 370 & Armada XP

Please note that the current v1 support has this restuction (same as
has Barebox version):

Not implemented: support for the register headers and secure headers
in v1 images

Tested on Marvell DB-78460-BP eval board.
Signed-off-by: NStefan Roese <sr@denx.de>
Tested-by: NLuka Perkov <luka@openwrt.org>

Signed-off-by: NStefan Roese <sr@denx.de>
Tested-by: NLuka Perkov <luka@openwrt.org>