- 23 6月, 2014 3 次提交
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由 Akshay Saraswat 提交于
While the Exynos5420 chip is used in both Smdk5420 and in the Peach-Pit line of devices, there could be other boards using the same chip, so a common configuration file is being added (exynos5420.h) as well as two common device tree files (exynos54xx.dtsi & exynos5420.dtsi). The peach board as declared in boards.cfg is a copy of smdk5420 declaration. The configuration files are similar, but define different default device trees, console serial ports and prompts. The device tree files for smdk5420 and peach-pit inherit from the same common file. Signed-off-by: NVadim Bendebury <vbendeb@chromium.org> Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com> Acked-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Akshay Saraswat 提交于
Macros defined in exynos5_setup.h specific to SMDK5420 are required for Peach-Pit too. Hence, replacing CONFIG_SMDK5420 with CONFIG_EXYNOS5420 to enable these macros for all the boards based on Exynos5420. Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com> Acked-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Akshay Saraswat 提交于
SPI recieve and transfer code in exynos_spi driver has a logical bug. We read data in a variable which can hold an integer. Then we assign this integer 32 bit value to another variable which has data type uchar. Latter represents a unit of our recieve buffer. Everytime when we write a value to our recieve buffer we step ahead by 4 units when actually we wrote to one unit. This results in the loss of 3 bytes out of every 4 bytes recieved. This patch intends to fix this bug. Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com> Acked-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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- 19 6月, 2014 1 次提交
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由 Przemyslaw Marczak 提交于
Generic board support is now enabled for Exynos 4, and if any init function returns an error then the init process is stopped. This makes a boot issue on the Trats and Trats2 devices. If the device is supplied by USB cable or an external power supply then it can't boot because function exynos_power_init returns an error. Now this function returns 0 if battery is not connected. Signed-off-by: NPrzemyslaw Marczak <p.marczak@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Piotr Wilczek <p.wilczek@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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- 18 6月, 2014 2 次提交
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由 Tushar Behera 提交于
We need to run 'usb start' as preboot command so that ethernet comes up during u-boot prompt. Signed-off-by: NTushar Behera <tushar.b@samsung.com> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Łukasz Majewski 提交于
Up till now goni's configuration has been stored at OneNAND. Since u-boot itself is now stored at eMMC it is more handy to store envs there as well. Signed-off-by: NLukasz Majewski <l.majewski@samsung.com> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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- 16 6月, 2014 1 次提交
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由 Łukasz Majewski 提交于
Modify GONI's configuration to utilize THOR downloader. Signed-off-by: NLukasz Majewski <l.majewski@samsung.com> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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- 13 6月, 2014 5 次提交
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由 Akshay Saraswat 提交于
Sometimes Read DQ and DQS are not in phase. Since, this phase shift differs from board to board, we need to calibrate it at DRAM init phase, that's read DQ calibration. This patch adds SW Read DQ calibration routine to compensate this skew. Signed-off-by: NAlim Akhtar <alim.akhtar@samsung.com> Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com> Acked-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Doug Anderson 提交于
when CLKM is running. If we stop CLKM when sampling it the glitches all go away, so we'll do that as per Samsung suggestion. We also check the "is it locked" bits of PHY_CON13 and loop until they show the the value sampled actually represents a locked value. It doesn't appear that the glitching and "is it locked" are related, but it seems wise to wait until the PHY tells us the value is good before we use it. In practice we will not loop more than a couple times (and usually won't loop at all). Signed-off-by: NDoug Anderson <dianders@chromium.org> Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com> Acked-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Akshay Saraswat 提交于
This patch intends to remove all code which enables hardware read leveling. All characterization environments may not cope up with h/w read leveling enabled, so we must disable this. Also, disabling h/w read leveling improves the MIF LVcc value (LVcc value is the value at which DDR will fail to work properly). Improving LVcc means we have enough voltage margin for MIF. When h/w leveling is enabled, we have almost zero volatge margin. Signed-off-by: NAlim Akhtar <alim.akhtar@samsung.com> Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com> Acked-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Akshay Saraswat 提交于
Passing fewer arguments is better and mem_iv_size is never used. Let's keep only one argument and make it cleaner. Signed-off-by: NHatim Ali <hatim.rv@samsung.com> Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com> Acked-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Minkyu Kang 提交于
This reverts commit eb0dd998.
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- 09 6月, 2014 5 次提交
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由 Masahiro Yamada 提交于
The symbol "_start" is defined twice in arch/arm/lib/vectors.S: around line 48 and line 54. If CONFIG_SYS_DV_NOR_BOOT_CFG is defined (as on calimain board), build fails: arch/arm/lib/vectors.S: Assembler messages: arch/arm/lib/vectors.S:54: Error: symbol `_start' is already defined make[1]: *** [arch/arm/lib/vectors.o] Error 1 make: *** [arch/arm/lib] Error 2 Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
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由 Mark Rutland 提交于
Currently cntvoff_el2 is initialised with an arbitrary bag of bits derived from the initial value of cnthctl_el2 on the current CPU. This is somewhat odd and problematic as some of these bits are UNKNOWN at reset and may differ across CPUs (which may cause an OS at EL1 to observe time going backwards across CPUs). This patch instead initialises cntvoff_el2 with xzr, giving the register a consistent value of zero on all CPUs. Signed-off-by: NMark Rutland <mark.rutland@arm.com> Acked-by: NMarc Zyngier <marc.zyngier@arm.com> Acked-by: NCatalin Marinas <catalin.marinas@arm.com> Cc: Scott Wood <scottwood@freescale.com> Cc: David Feng <fenghua@phytium.com.cn> Cc: Tom Rini <trini@ti.com> Acked-by: NDavid.Feng <fenghua@phytium.com.cn>
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由 Chao Fu 提交于
Add QSPI support for VF610TWR, such as clock and iomux. Signed-off-by: NAlison Wang <Huan.Wang@freescale.com> Signed-off-by: NChao Fu <b44548@freescale.com>
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由 Alison Wang 提交于
Add PAD_CTL_DSE_150ohm and PAD_CTL_PUS_22K_UP for VF610 in IOMUX_PAD structure. Signed-off-by: NAlison Wang <Huan.Wang@freescale.com>
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由 Alison Wang 提交于
Add Freescale QSPI driver support for VF610. Signed-off-by: NAlison Wang <Huan.Wang@freescale.com> Signed-off-by: NChao Fu <b44548@freescale.com>
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- 08 6月, 2014 1 次提交
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由 Albert ARIBAUD 提交于
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- 07 6月, 2014 22 次提交
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由 Tom Rini 提交于
This family is supported by the TPS65218 PMIC. Implement a scale_vcores to set the MPU and CORE voltage correctly to the max frequency that is supported (and what we will be scaling them to in setup_dplls()). Signed-off-by: NTom Rini <trini@ti.com>
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由 Tom Rini 提交于
Add a driver for the TPS65218 PMIC which is used by TI AM43xx SoCs and may be used by TI AM335x SoCs. Signed-off-by: NTom Rini <trini@ti.com>
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由 Tom Rini 提交于
Similar to OMAP4/5 we need to scale the voltage up prior to changing the clock frequencies up higher. Add a similar hook to start with. Signed-off-by: NTom Rini <trini@ti.com>
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由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@ti.com>
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由 Hannes Petermaier 提交于
Cc: trini@ti.com Signed-off-by: NHannes Petermaier <oe5hpm@oevsv.at>
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由 Hannes Petermaier 提交于
in almost all cases we need the i2c commands within the u-boot shell. So we enable them within the common section. Cc: trini@ti.com Signed-off-by: NHannes Petermaier <oe5hpm@oevsv.at>
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由 Hannes Petermaier 提交于
if we have no NAND-Chip, we don't need the gpmc-controller and therefore is no need to init it. Cc: trini@ti.com Signed-off-by: NHannes Petermaier <oe5hpm@oevsv.at>
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由 Hannes Petermaier 提交于
Cc: trini@ti.com Signed-off-by: NHannes Petermaier <oe5hpm@oevsv.at>
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由 Hannes Petermaier 提交于
Signed-off-by: NHannes Petermaier <oe5hpm@oevsv.at>
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由 Hannes Petermaier 提交于
For usage of timer6 within B&R we need this defines to enable clock modules and clk-source. Also the 'Timer register bits' are expanded. By the way we add defines for all timers within AM335x SoC. Cc: trini@ti.com Signed-off-by: NHannes Petermaier <oe5hpm@oevsv.at>
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由 Lokesh Vutla 提交于
After enabling a module, SW has to wait on IDLEST bit until it is Fully functional. This wait is missing for UART module and there is a immediate access of UART registers after this. So there is a chance of hang on this module( This can happen when we are running from MPU SRAM). So waiting for IDLEST bit. Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
loadbootenv expects devtype variable to be set. This is missing in mmcboot command. With this the following error comes: U-Boot# run mmcboot mmc0 is current device SD/MMC found on device 0 ** Bad device usb 0 ** ** Bad device usb 0 ** Fixing this by setting devtype as mmc. Reported-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Jeroen Hofstee 提交于
commit a0a37183 "ARM: omap: merge GPMC initialization code for all platform" needs CONFIG_NOR, CONFIG_NAND or CONFIG_CMD_ONENAND to be set to access flash. Add CONFIG_NAND for tam3517 derived boards to prevent the following error: "nand: error: Unable to find NAND settings in GPMC Configuration - quitting" cc: Stefano Babic <sbabic@denx.de> Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl>
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由 WingMan Kwok 提交于
Enable support of nand ecclayout command. Acked-By: NMurali Karicheri <m-karicheri2@ti.com> Acked-by: NVitaly Andrianov <vitalya@ti.com> Signed-off-by: NWingMan Kwok <w-kwok2@ti.com> Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>
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由 Murali Karicheri 提交于
Currently PWREMU_MGMT is not configured in the Linux generic UART driver as this register seems to be specific TI UART IP. So this needs to be enabled in u-boot to use UART1 from kernel space. Acked-By: NVitaly Andrianov <vitalya@ti.com> Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com> Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>
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由 Tom Rini 提交于
With the changes to the i2c framework (and adopting the omap24xx_i2c driver to them) we can no longer call i2c functions prior to gd having been set and cleared. When SPL booting, this is handled by setting gd to point to SRAM in s_init. However in the cases where we are loaded directly by ROM (memory mapped NOR or QSPI) we need to make use of the normal hooks to slightly delay these calls. Signed-off-by: NTom Rini <trini@ti.com>
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由 Tom Rini 提交于
We have two contexts for booting these platforms. One is SPL which is roughly: reset, cpu_init_crit, lowlevel_init, s_init, sdram_init, _main, board_init_f from SPL, ... then U-Boot loads. The other is a memory-mapped XIP case (NOR or QSPI) where we do not run an SPL. In this case we go, roughly: reset, cpu_init_crit, lowlevel_init, s_init, _main, regular board_init_f. In the first case s_init will set a valid gd and then be able to call sdram_init which in many cases will need i2c (which needs a valid gd for gd->cur_i2c_bus). In this second case we must (and are able to and should) defer sdram_init() into dram_init() called by board_init_f as gd will have been set in _main and cleared in board_init_f. Signed-off-by: NTom Rini <trini@ti.com>
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由 Sourav Poddar 提交于
The patch populates the slave data which will be used by flash driver to set the flash quad enable bit. Signed-off-by: NSourav Poddar <sourav.poddar@ti.com>
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由 Sourav Poddar 提交于
The ePOS EVM and EVM SK have QSPI as an option to boot. Add a qspiboot target that utilizes QSPI for env and so forth as an example of best practices. As QSPI is booted from directly we need to chang CONFIG_SYS_TEXT_BASE. Note that on ePOS EVM the QSPI and NAND are mutually exclusive choices we need to handle that elsewhere, once NAND support is also added. Signed-off-by: NSourav Poddar <sourav.poddar@ti.com> Signed-off-by: NTom Rini <trini@ti.com>
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由 pekon gupta 提交于
updates documentation with explanation on how to select ECC schemes. Signed-off-by: NPekon Gupta <pekon@ti.com>
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由 pekon gupta 提交于
This patch add support for BCH16_ECC to omap_gpmc driver. *need to BCH16 ECC scheme* With newer SLC Flash technologies and MLC NAND, and large densities, pagesizes Flash devices have become more suspectible to bit-flips. Thus stronger ECC schemes are required for protecting the data. But stronger ECC schemes have come with larger-sized ECC syndromes which require more space in OOB/Spare. This puts constrains like; (a) BCH16_ECC can correct 16 bit-flips per 512Bytes of data. (b) BCH16_ECC generates 26-bytes of ECC syndrome / 512B. Due to (b) this scheme can only be used with NAND devices which have enough OOB to satisfy following equation: OOBsize per page >= 26 * (page-size / 512) Signed-off-by: NPekon Gupta <pekon@ti.com>
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由 pekon gupta 提交于
GPMC can support simultaneous processing of 8 512Byte data chunks, in parallel Signed-off-by: NPekon Gupta <pekon@ti.com>
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