Today in initr_reloc_global_data() we use some non-obvious tests to
determine if we need to relocate the env_addr within gd or not.  In
order to facilitate migration of other symbols to Kconfig we need to
introduce a new symbol for this particular use case.

Cc: Wolfgang Denk <wd@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NTom Rini <trini@konsulko.com>

Support tinker-s board. The board is equivalent of tinker board
except of emmc.

TODO:
- support of usb current burst when the board is powered from pc
Signed-off-by: NMichael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

ROC-RK3308-CC is a rk3308 based board designed by
Firelfy, with eMMC and 256MB DDR3 and RTL8188 Wifi
on board.
Signed-off-by: NAndy Yan <andy.yan@rock-chips.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

Add support for rk3308 evaluation board.
Signed-off-by: NAndy Yan <andy.yan@rock-chips.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

rockpro64 needs to setup I/O domains in order for USB to work in u-boot.
Since we currently don't have a driver to do that, split it into its own
board file and initialize I/O domains here.
Signed-off-by: NVasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

Enable TPL for rock960 like other rk3399 boards.
Signed-off-by: NPeter Robinson <pbrobinson@gmail.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

roc-rk3399-pc_defconfig is committed in below

commit <8a681f4c> ("rockchip: rk3399:
Add ROC-RK3399-PC support")

which doesn't follow the existing defconfigs on rk3399.

So, rename as followed with other rk3399 defconfigs.

Cc: Levin Du <djw@t-chip.com.cn>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

The px30 evb is an evaluation board for the px30 together with a dsi-
connected display. This adds board and config files for it.
Signed-off-by: NHeiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

RK3328 has a similar controller and phy with PX30, so we can use the
common driver for it and remove the duplicate codes.
Signed-off-by: NYouMin Chen <cym@rock-chips.com>
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>

Move this symbol to Kconfig.  As part of this we can drop a UBI-specific
symbol that was a stop-gap for not having this particular symbol in
Kconfig.
Signed-off-by: NTom Rini <trini@konsulko.com>

This board is setting CONFIG_ENV_IS_IN_SPI_FLASH in the header rather
than defconfig, fix.

Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: NTom Rini <trini@konsulko.com>

This board is setting CONFIG_ENV_IS_IN_MMC in the header rather than
defconfig, fix.

Cc: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: NTom Rini <trini@konsulko.com>

Rsync all defconfig files using moveconfig.py
Signed-off-by: NTom Rini <trini@konsulko.com>

This patch enable TPL support for firefly-rk3288 board, which works ths
same way with other RK3288 board like Tinker, evb.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>

Use the same SPL_STACK_R_ADDR in Kconfig instead of each board config;
default to 0x4000000(64MB) instead of 0x80000(512KB) for this address
can support all the SoCs including those may have only 64MB memory, and
also reserve enough space for atf, kernel(in falcon mode) loading.

After the ATF entry move to 0x40000, the stack from 0x80000 may be override
when loading ATF bl31.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>

We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code,
and when we introduce the TPL, the SPL space is in DRAM, we reserve
space to avoid SPL text overlap with ATF bl31.

Now we decide to move ATF entry point to 0x40000 instead of 0x1000,
so that the SPL can have 0x4000 as code size and no need to reserve
space or relocate before loading ATF.

The mainline ATF has update since:
0aad563c rockchip: Update BL31_BASE to 0x40000
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>

We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code,
and when we introduce the TPL, the SPL space is in DRAM, we reserve
space to avoid SPL text overlap with ATF bl31.

Now we decide to move ATF entry point to 0x40000 instead of 0x1000,
so that the SPL can have 0x4000 as code size and no need to reserve
space or relocate before loading ATF.

The mainline ATF has update since:
0aad563c rockchip: Update BL31_BASE to 0x40000
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>

We use to reserve IRAM to avoid the SPL text overlap with ATF M0 code,
and when we introduce the TPL, the SPL space is in DRAM, we reserve
space to avoid SPL text overlap with ATF bl31.

Now we decide to move ATF entry point to 0x40000 instead of 0x1000,
so that the SPL can have 0x4000 as code size and no need to reserve
space or relocate before loading ATF.

The mainline ATF has update since:
0aad563c rockchip: Update BL31_BASE to 0x40000
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>

Specification
- Rockchip RK3399
- LPDDR4
- TF sd scard slot
- eMMC
- M.2 B-Key for 4G LTE
- AP6256 for WiFi + BT
- Gigabit ethernet
- HDMI out
- 40 pin header
- USB 2.0 x 2
- USB 3.0 x 1
- USB 3.0 Type-C x 1
- TYPE-C Power supply

Commit details of rk3399-leez-p710.dts sync from linus tree for Linux 5.4-rc1:
"arm64: dts: rockchip: Add dts for Leez RK3399 P710 SBC"
(sha1: 	fc702ed49a8668a17343811ee28214d845bfc5e6)
Signed-off-by: NAndy Yan <andyshrk@gmail.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

Rename the CONFIG_SECURE_BOOT name to CONFIG_NXP_ESBC to avoid
conflicts with UEFI secure boot.
Signed-off-by: NUdit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>

Rename CONFIG_SECURE_BOOT to CONFIG_NXP_ESBC to avoid conflict
with UEFI secure boot.
Signed-off-by: NUdit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>

The SPL FIT will only have one DTB, so remove support for multi-DTB. This
also removes an early access to EEPROM used to select the DTB that is not
valid in SPL at the point at which it is accessed, that always returns
false for GP devices and causes a firewall expection on HS.
Signed-off-by: NAndrew F. Davis <afd@ti.com>
Reviewed-by: NLokesh Vutla <lokeshvutla@ti.com>

The SPL is too tight, and it cannot start any longer.  To
help reduce the size of SPL, we need to remove some non-critical
features.

This patch removes SPL_GPIO_SUPPORT to free up some operating space.
Signed-off-by: NAdam Ford <aford173@gmail.com>

The SPL is too tight, and it cannot start any longer.  To
help reduce the size of SPL, we need to remove some non-critical
features.

This reverts commit 66063a7c.
Signed-off-by: NAdam Ford <aford173@gmail.com>

Enable AVS Class 0 & dependent config options.
Signed-off-by: NKeerthy <j-keerthy@ti.com>

Enable AVS class 0 support for the R5 SPL bootloader.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Signed-off-by: NKeerthy <j-keerthy@ti.com>

TPS62363 is used to control the MPU_VDD voltage, so enable the driver
for this.
Signed-off-by: NTero Kristo <t-kristo@ti.com>
Signed-off-by: NKeerthy <j-keerthy@ti.com>

This adds platform code and the device tree for the Phytium Durian Board.
The initial support comprises the UART and the PCIE.

Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: NSteven Hao <liuhao@phytium.com.cn>

Rsync all defconfig files using moveconfig.py
Signed-off-by: NTom Rini <trini@konsulko.com>

add DM PCI support on the socrates board.
use PCIE_FSL now.
Signed-off-by: NHeiko Schocher <hs@denx.de>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

switch to DM_SERIAL support.
Signed-off-by: NHeiko Schocher <hs@denx.de>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

enable DM I2C support for the socrates board.
Signed-off-by: NHeiko Schocher <hs@denx.de>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

disable video, as not really needed longer.
Signed-off-by: NHeiko Schocher <hs@denx.de>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

add some defines and get rid of USB warning.
Signed-off-by: NHeiko Schocher <hs@denx.de>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

enable CONFIG_DM for the socrates board.
Signed-off-by: NHeiko Schocher <hs@denx.de>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

add phy-reset-gpios to reset phy
Add board_phy_config to configure phy
Enable DM_ETH
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Support pinctrl/clk/sdhc, include ddr4 timing data.

Log:
U-Boot SPL 2019.10-rc3-00356-g497c500423-dirty (Sep 16 2019 - 10:54:58 +0800)
Normal Boot
Trying to boot from BOOTROM
image offset 0x8000, pagesize 0x200, ivt offset 0x0

U-Boot 2019.10-rc3-00356-g497c500423-dirty (Sep 16 2019 - 10:54:58 +0800)

CPU:   Freescale i.MX8MNano rev1.0 at 24 MHz
Reset cause: POR
Model: NXP i.MX8MNano DDR4 EVK board
DRAM:  2 GiB
MMC:   FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... *** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Net:   No ethernet found.
Hit any key to stop autoboot:  0
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

with u-boot,dm-spl added for imx8qm-pm node, and SPL_SIMPLE_BUS enabled,
the bind and probe code in board file could be removed.

Also we need to enlarge SYS_MALLOC_F_LEN to avoid calloc fail.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

This board appears to be very near its size limit and cannot accept the
new checking code in libfdt. Disable this code so this the board can
continue to build.
Signed-off-by: NSimon Glass <sjg@chromium.org>

We have once again reached a point where this board does not build in
some cases with supported toolchains due to reaching a size constraint.
To regain some space, disable support for Plan 9 / RTEMS images with the
bootm command.
Acked-by: NStefano Babic <sbabic@denx.de>
Signed-off-by: NTom Rini <trini@konsulko.com>