Add support for SAMA7G5 GMAC.
Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>

clk_set_rate() returns the set rate in case of success and a
negative number in case of failure. Consider failure only the
negative numbers.

Fixes: 3ef64444 ("dm: net: macb: Implement link speed change callback")
Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>

Different implementation of USER IO register needs different
mapping for bit fields of this register. Add implementation
for this and, since clken is part of USER IO and it needs to
be activated based on per SoC capabilities, add caps in
macb_config where clken specific information needs to be filled.
Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>

Because ATMEL_BASE_ROM is defined to 0x100000, it already points
to the begin of the index table for 512 byte sectors correction.
Thus its offset must be zero and the index of the table for 1024
byte sectors must start at offset 0x8000.
Signed-off-by: NKai Stuhlemmer (ebee Engineering) <kai.stuhlemmer@ebee.de>
[ta: update commit message]
Signed-off-by: NTudor Ambarus <tudor.ambarus@microchip.com>

Offsets are described in the datasheet at section:
"11.4.4.2 NAND Flash Boot: PMECC Error Detection and Correction".

For testing I "injected" bit flips into u-boot NAND memory area,
and then read back. PMECC could not correct the errors. With the
offsets updated everything is fine.

Fixes: 3225f34e ("ARM: atmel: add sama5d3xek support")
Signed-off-by: NTudor Ambarus <tudor.ambarus@microchip.com>

When CONFIG_ATMEL_NAND_HW_PMECC is set, CONFIG_PMECC_CAP defaults
to the value of 2. At the conversion to Kconfig for the PMECC config
values, some boards/defconfigs were wrongly configured.
Update CONFIG_PMECC_CAP to the PMECC_CAP value before the conversion.

Fixes: 49ad4029 ("ARM: at91: Convert SPL_GENERATE_ATMEL_PMECC_HEADER to Kconfig")
Signed-off-by: NTudor Ambarus <tudor.ambarus@microchip.com>

SPL_GENERATE_ATMEL_PMECC_HEADER selects:
ATMEL_NAND_HWECC [=y] && ATMEL_NAND_HW_PMECC [=y].

With the removal of SPL_GENERATE_ATMEL_PMECC_HEADER,
ATMEL_NAND_HW_PMECC and ATMEL_NAND_HWECC were no longer
selected. Also, when the SPL_GENERATE_ATMEL_PMECC_HEADER was removed,
the configs were not updated using savedefconfig, thus the
'commit d168bcb6 ("configs: Resync with savedefconfig")'
further removes the CONFIG_PMECC_CAP value.

Update defconfigs and add CONFIG_ATMEL_NAND_HW_PMECC,
which selects ATMEL_NAND_HWECC, in order to restore NAND PMECC
support. Restore CONFIG_PMECC_CAP value.

Fixes: 57f76c2a ("configs: at91: remove SPL_GENERATE_ATMEL_PMECC_HEADER from non-nand configs")
Signed-off-by: NTudor Ambarus <tudor.ambarus@microchip.com>

Implement drive strength support, by preserving the same bindings
as in Linux.
Signed-off-by: NEugen Hristev <eugen.hristev@microchip.com>

Use dev_read_prop instead of using the fdt_read_property which
reads from the GD struct's fdt.
This way the node is accessed via the device config instead of the
global struct, which makes code more portable and GD independent.
Signed-off-by: NEugen Hristev <eugen.hristev@microchip.com>

Add drive strength property which is equivalent with the one in Linux
Signed-off-by: NEugen Hristev <eugen.hristev@microchip.com>

Update license header to SPDX style
Signed-off-by: NEugen Hristev <eugen.hristev@microchip.com>

Fix typo.
Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>

Add support for DLL setup on KSZ9131.
Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>

- R-Car pinctrl updates

- Update qemu-riscv.rst build instructions.
- Add support for SPI on Kendryte K210.
- Add Microchip PolarFire SoC Icicle Kit support.
- Add support for an early timer.
  - Select TIMER_EARLY to avoid infinite recursion for Trace.

Pull request for documentation tag doc-2021-04-rc1

* document man-page base command
* move README.fdt-overlays to HTML documentation
* add synopsis for pstore command

- Assorted testing improvements and fixes
- Assorted code cleanups

Remove the leading "0x" from rpc node to fix the below dtc warning:

Warning (simple_bus_reg): Node /soc/rpc@0xee200000 simple-bus unit
address format error, expected "ee200000"
Signed-off-by: NLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Implement get_pin_muxing() callback so that pinmux status
command can be used on Renesas platforms.
Signed-off-by: NLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: NBiju Das <biju.das.jz@bp.renesas.com>

By default on startup all the pin types are configured to
PINMUX_TYPE_NONE (in sh_pfc_map_pins()), when pin is set as GPIO the
pin type is updated to PINMUX_TYPE_GPIO. But the type is not updated
when the pin is set as a function in sh_pfc_pinctrl_pin_set() or
sh_pfc_pinctrl_group_set() calls (these calls only set the MUX if
the pin type is PINMUX_TYPE_NONE ie unused).

So with the current implementation pin functionality could be overwritten
silently, for example if the same pin is added for SPI and serial.

This patch makes sure of updating pin type after every successful call to
sh_pfc_config_mux() and thus fixing from pin functionality to be
overwritten. Also a warning message is printed if the current pin is being
overwritten before abort.

This also avoids pin re-muxing to same type that is for example from
command line device is asked to re-probe/select (mmc dev x) we return
early with success in this case as the pin is already muxed.
Signed-off-by: NLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: NBiju Das <biju.das.jz@bp.renesas.com>

This doc describes the procedure to build, flash and
boot Linux using U-boot on Microchip MPFS Icicle Kit.
Signed-off-by: NPadmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>
Reviewed-by: NBin Meng <bin.meng@windriver.com>

This patch adds Microchip MPFS Icicle Kit support. For now, only
NS16550 Serial, Microchip clock, Cadence eMMC and MACB drivers are
enabled. The Microchip MPFS Icicle defconfig by default builds
U-Boot for S-Mode because U-Boot on Microchip PolarFire SoC will run
in S-Mode as payload of HSS + OpenSBI.
Signed-off-by: NPadmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>
Reviewed-by: NBin Meng <bin.meng@windriver.com>
Tested-by: NBin Meng <bin.meng@windriver.com>

Add device tree for Microchip PolarFire SoC Icicle Kit.
Signed-off-by: NPadmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>
Reviewed-by: NBin Meng <bin.meng@windriver.com>

Add clock driver code for the Microchip PolarFire SoC. This driver
handles reset and clock control of the Microchip PolarFire SoC device.
Signed-off-by: NPadmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>
Tested-by: NBin Meng <bin.meng@windriver.com>

Read phy address from device tree and use it to find the phy device
if not found then search in the range of 0 to 31.
Signed-off-by: NPadmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>
Reviewed-by: NBin Meng <bin.meng@windriver.com>
Tested-by: NBin Meng <bin.meng@windriver.com>

Enable 32-bit or 64-bit DMA in the macb driver based on the macb
hardware compatibility and it is configured with structure macb_config
in the driver.

The Microchip PolarFire SoC Memory Protection Unit(MPU) gives the 64-bit
DMA access with the GEM, the MPU transactions on the AXI bus is 64-bit
not 32-bit So 64-bit DMA is enabled for the Microchip PolarFire SoC GEM.
Signed-off-by: NPadmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>
Tested-by: NBin Meng <bin.meng@windriver.com>

dma_addr_t holds any valid DMA address. If the DMA API only uses 32/64-bit
addresses, dma_addr_t need only be 32/64 bits wide.
Signed-off-by: NPadmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>
Reviewed-by: NBin Meng <bin.meng@windriver.com>
Reviewed-by: NRick Chen <rick@andestech.com>

Added support for timer_early_get_count() and timer_early_get_rate()
This is mostly useful in tracing.
Signed-off-by: NPragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: NRick Chen <rick@andestech.com>

When tracing functions is enabled this adds calls to
__cyg_profile_func_enter() and __cyg_profile_func_exit() to the traced
functions.

__cyg_profile_func_enter() and __cyg_profile_func_exit() invoke
timer_get_us() to record the entry and exit time.

initr_dm() will make gd->dm_root = NULL and gd->timer = NULL, so
timer_get_us() -> get_ticks() -> dm_timer_init() will lead to an
indefinite recursion.

So select TIMER_EARLY when tracing got enabled.
Signed-off-by: NPragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NRick Chen <rick@andestech.com>

This enables configs necessary for using SPI. The environment is saved to
the very end of SPI flash. This is unlikely to be overwritten unless the
entire flash is reprogrammed.

This also supplies a default bootcommand. It loads an image and device tree
from the first partition of the MMC. This is a minimal/least effort
bootcmd, so suggestions (especially in the form of patches) are welcome. I
didn't set up distro boot because I think it is unlikely that any
general-purpose linux distros will ever be ported to this board.
Signed-off-by: NSean Anderson <seanga2@gmail.com>
Tested-by: NChrstopher Obbard <obbardc@gmail.com>
Reviewed-by: NRick Chen <rick@andestech.com>

Latest opensbi uses generic platform for Qemu. Update the build
instructions.
Signed-off-by: NAtish Patra <atish.patra@wdc.com>
Reviewed-by: NBin Meng <bin.meng@windriver.com>
Reviewed-by: NRick Chen <rick@andestech.com>

fit_print_contents prints similar fit information as printed in bootm stages.
Removing this API reduces redundancy & provides improvement in boottime.
Signed-off-by: NRavik Hasija <rahasij@linux.microsoft.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Change 2 typo error in CONFIG_LIB_ELF description:
- Supoort => Support
- fir => for
Signed-off-by: NPatrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Provide a unit test for printing via pr_err() and pr_cont().
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: NSimon Glass <sjg@chromium.org>

With commit d094a073 ("log: allow for message continuation") we have
defined a special log level and category for message continuation. Let's
have a macro for using these.

If logging is enabled log_cont() will create a continuation log output with
the same logging level and category as the previous message.

If logging is not enabled, log_cont() will print like printf().

Provide macros for logging levels LOG_EMERG, LOG_ALERT, LOG_CRIT.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Change debug_cond() such that it can be used instead of a function like
debug().
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The macro BIT_MASK is already defined in include/linux/bitops.h. To avoid
name collisions rename BIT_MASK() in drivers/ram/k3-j721e/lpddr4_private.h
to LPDDR4_BIT_MASK().

Remove superfluous parantheses.
Remove superfluous comparison to 0.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: NSimon Glass <sjg@chromium.org>

log.h and dm/devres.h are U-Boot includes. So placing them
behind #ifndef __UBOOT__ does not make any sense.

Fixes: f7ae49fc ("common: Drop log.h from common header")
Fixes: 61b29b82 ("dm: core: Require users of devres to include the header")
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: NSimon Glass <sjg@chromium.org>

In contrast to the C99 standard [1] our putc() takes only one argument.

[1] ISO/IEC 9899:1999
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

Our ctype.h is in include/linux/
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>