Fix my fragments to list all files in the repo.

Also fix path to for Xilinx Zynq SoC (mach-zynq)
It should be the part of
"ARM: zynq: move SoC sources to mach-zynq"
(sha1: 0107f240)

And cover dts files in board MAINTAINERS files.
Reported-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

There is an issue to recognize zynq or zynqmp image because header
checking is just the same. That's why zynqmp images are recognized as
zynq one.
Check unused fields which are initialized to zero in zynq format
(__reserved1 0x38 and __reserved2 0x44) which are initialized for
zynqmp. This should ensure that images are properly recognized by:
./tools/mkimage -l spl/boot.bin

Also show image type as ZynqMP instead of Zynq which is confusing.
Reported-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Tested-by: NAlexander Graf <agraf@suse.de>

This patch adds new command "zynqmp" to handle zynqmp
specific commands like "zynqmp secure". This secure command is
used for verifying zynqmp specific secure images. The secure
image can either be authenticated or encrypted or both encrypted
and authenticated. The secure image is prepared using bootgen
and will be in xilinx specific BOOT.BIN format. The optional
key can be used for decryption of encrypted image if user
key was specified while creation BOOT.BIN.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

ZynqMP Emulation board is no longer tested and there is no reason to
keep maintaining it.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The vcu disable bit in efuse ipdisable register is valid only
if PL powered up so, consider PL powerup status for determing
EG/EV part. If PL is not powered up, ignore EG/EV part of string.
The PL powerup status will be filled by pmufw based on PL PROGB
status in the 9th bit of version field.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

This patch print pl clocks (pl0...pl3) and watchdog
clock using clk dump.
Signed-off-by: NVipul Kumar <vipulk@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

NAND erase was not happening for size 1GiB or more. Erase
command was executing successfully but in actual, it was not
erasing.
This patch fixed erase issue for 1 GiB or more size nand.
Signed-off-by: NVipul Kumar <vipulk@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Use appended dtb which is default option for zynq boards.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The same command should be used for x16 configuration.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

This patch changed CONFIG_SYS_MEMTEST_SCRATCH address to the
accessible DDR address used by alternate memory test.
Before this, 0xfffc0000 address was used, which is the OCM
address and not enabled in MMU table. So, whenever trying
to access 0xfffc0000 address, got Synchronous Abort exception.

After changing CONFIG_SYS_MEMTEST_SCRATCH address, alternate
memory test is working fine.
Signed-off-by: NVipul Kumar <vipulk@xilinx.com>
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Enable watchdog with reset-on-timeout feature.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Watchdog is only enabled in full u-boot. Adoption for SPL should be also
done because that's the right place where watchdog should be enabled.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

This IP can be found on Zynq and ZynqMP devices.
The driver was tested with reset-on-timeout; feature.

Also adding WATCHDOG symbol to Kconfig because it is required.
Signed-off-by: NShreenidhi Shedi <imshedi@gmail.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

watchdog clock is also connected to cpu 1X clocksource.

Zynq> clk dump
...

Before:
      swdt          4294967290
After:
      swdt           111111110
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

As of now newer pmufw is keeping old interfaces. That's why permit
u-boot to run on newer version. Recommended version will be setup later.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

This patch bypasses phy detection logic for GMII interface
and just depend on phy address received from DT. This patch
is required as phy detection logic is different for some phys
like xilinx phy which can be connected over SGMII and GMII
interface.
This fixes the issue of ethernet failures when xilinx phy is
connected over GMII interface.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

This patch is adding support to switch to EL1 while loading an EL1
application with u-boot running at EL above EL1 in aarch64 mode.
Signed-off-by: NNitin Jain <nitinj@xilinx.com>
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

It helps with debugging.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Enable missing driver on this board.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Check !desc earlier to simplify code.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Acked-by: NSimon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Reviewed-by: NSimon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>

Make defconfigs up2date with current location.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Use zynqmp clock driver instead of fixed clocks.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Enable Driver Model and Device-tree support for omapl138 board
in U-Boot. Also enable DM_SERIAL and DM_I2C.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Sync dts from Linux 4.16 and also add u-boot specific
dtsi for OMAPl138 board.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Commit 6aa4ad8e ("Convert CONFIG_SOC_DA8XX et al to Kconfig")
converted SOC_DA8XX to Kconfig but missed enabling DDR_INIT for
SOC_DA8XX, which broke OMAPL138 to boot.

Commit 2e879805 ("davinci: Fix omapl138_lcdk builds") disabled
DDR_INIT for all DA850 SoCs. This failed all DA850 boards to boot
as ddr is not being initialized.

Enable SYS_DA850_DDR_INIT for DA8XX so that all DA850 and OMAPL138
will have ddr initialized

Fixes: 2e879805 ("davinci: Fix omapl138_lcdk builds")
Fixes: 6aa4ad8e ("Convert CONFIG_SOC_DA8XX et al to Kconfig")
Reported-by: NSekhar Nori <nsekhar@ti.com>
Tested-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: NDavid Lechner <david@lechnology.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

With gpio devices getting created in SPL, the size of the heap is
no longer sufficient. Therefore, increase SPL_SYS_MALLOC_F_LEN
to 0x1000.
Signed-off-by: NFaiz Abbas <faiz_abbas@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

With DM enabled in SPL, DM_FLAG_PRE_RELOC is required for
the omap_gpio driver to be bound to the gpio devices.

Therefore, add DM_FLAG_PRE_RELOC flag to the omap_gpio driver.
Signed-off-by: NFaiz Abbas <faiz_abbas@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

scripts/check-config.sh exits successfully and silently without doing
any checks when the 'comm' command is not found.

The problem triggers from the command around line 39:

  comm -23 ${suspects} ${ok} >${new_adhoc}

This statement fails when 'comm' is not in $PATH, creating an empty
${new_adhoc} file. But the script continues and the following line,
which is supposed to detect an error:

  if [ -s ${new_adhoc} ]; then

will always be false since the file is empty, and the script will exit
successfully as if everything were OK.

The case where 'comm' in not in $PATH is not theoretical. It used to
happen on yocto until a recent fix [0], and still happens on the
current stable branch (rocko).

Fix by setting the errexit flag to exit with error when a statement
fails, so that at least the problem is noticed.

For additional safety also set the nounset flag to detect expansion
errors.

[0] http://git.yoctoproject.org/cgit/cgit.cgi/poky/commit/?id=fe0b4cb5b48580d4a3f3c0eb82bfa6f1b13801e4Signed-off-by: NLuca Ceresoli <luca@lucaceresoli.net>
Reviewed-by: NSimon Glass <sjg@chromium.org>

commit 1601dd97 ("davinci: omapl138_lcdk: increase PLL0 frequency")
changed the PLL0 frequency to 456MHz, which is needed for the LCDC IP
block. However, in doing so, it caused the PLLOUT clock to be outside
of the allowable specifications given in the OMAP-L138 data sheet. (It
says PLLOUT must be 600MHz max). It also uses a PLLM value outside of
the range given in the TRM (it says PLLM must in the range 0 to 0x1f).

So here is what we have currently:

PLLOUT = 24 / (0 + 1) * (37 + 1) = 912MHz (out of spec)
         ^     ^         ^
       CLKIN PREDIV    PLLM (out of spec)

input to PLLDIVn = 912 / (1 + 1) = 456MHz (desired result)
                    ^     ^
                 PLLOUT POSTDIV

This changes the PLLM value to 18 and the POSTDIV value to 0 so that
PLLOUT is now within specification but we still get the desired
result.

PLLOUT = 24 / (0 + 1) * (18 + 1) = 456MHz (within spec)
         ^     ^         ^
       CLKIN PREDIV     PLLM

input to PLLDIVn = 456 / (0 + 1) = 456MHz (desired result)
                    ^     ^
                 PLLOUT POSTDIV

Fixes: 1601dd97 ("davinci: omapl138_lcdk: increase PLL0 frequency")
Signed-off-by: NDavid Lechner <david@lechnology.com>
Reported-by: NSekhar Nori <nsekhar@ti.com>
Tested-by: NSekhar Nori <nsekhar@ti.com>

Add basic tests for the spi_flash subsystem.
Signed-off-by: NLiam Beguin <liambeguin@gmail.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Last user of this driver went away in October 2014 in
commit d58a9451 ("ppc/arm: zap EMK boards").
Signed-off-by: NTuomas Tynkkynen <tuomas@tuxera.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

In

	if (a > =0) {...}
	else (a < 0) {...}

the second logical constraint is superfluous.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

In

	int ret = A;
	ret = B;

the first assignment has not effect.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

The lan75xx and lan78xx drivers need to drive their phy via the generic
phylib framework. Let's reflect that dependency in Kconfig, so that we
don't get build errors when phylib does not get selected.
Signed-off-by: NAlexander Graf <agraf@suse.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

In the efi_loader main loop we call eth_rx() occasionally. This rx function
might end up calling into devices that haven't been initialized yet,
potentially resulting in a lot of transfer timeouts.

Instead, let's make sure the ethernet device is actually initialized before
reading from or writing to it.
Signed-off-by: NAlexander Graf <agraf@suse.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

The "net_try_count" counter starts from "1".
And the "retrycnt" contains requested amount of retries.

With current logic, that means that the actual retry amount
will be one time less then what we set in "netretry" env.
For example setting "netretry" to "once" will make "retrycnt"
equal "1", so no retries will be triggered at all.

Fix the logic by changing the statement of "if" condition.
Signed-off-by: NLeonid Iziumtsev <leonid.iziumtsev@se.atlascopco.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Current Cortina phy driver assumes that firmware upload
is required during initialization and is dependent
on presence of corresponding macros like CONFIG_CORTINA_FW_ADDR
for compilation.

But Cortina phy has provision to store phy firmware in
attached dedicated EEPROM. And boards designed with such
EEPROM does not require firmware upload.

Add CORTINA_NO_FW_UPLOAD option in cortina.c to support
such boards.
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Update get_phy_id() implementation in cortina.c to check
for Cortina_phy by comparing device phy_id with cortina phy_id
instead of relying on presence of CORTINA macros.

This will allow get_phy_id to work with non-cortina phy devices
which might have same phy address as Cortina device but on
different  bus.
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Add configurations for PFE.
Signed-off-by: NCalvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: NAnjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>