- 23 4月, 2014 36 次提交
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由 Nikhil Badola 提交于
Increase TXFIFOTHRES field value in TXFILLTUNING register of usb for T4 Rev 2.0. This decreases data burst rate with which data packets are posted from the TX latency FIFO to compensate for latencies in DDR pipeline during DMA. This avoids Tx buffer underruns and leads to successful usb writes Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: NNikhil Badola <nikhil.badola@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
T1040RDB and T1042RDB_PI has CPLD. Here CPLD controls board mux/features. This support of CPLD includes - files and register defintion - Commands to swtich alternate bank and default bank Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Codrin Ciubotariu 提交于
T1040RDB and T1040QDS boards have an integrated l2 switch. The switch needs a MAC address for Layer 2 protocols (MSTP, LLDP, LACP, etc). Setting a MAC address on l2switchaddr will add a MAC in device-tree, under node l2switch. Signed-off-by: NCodrin Ciubotariu <codrin.ciubotariu@freescale.com> Cc: York Sun <yorksun@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
We use dynamical mtdparts partition instead of directly puting mtd partitions nodes in device tree. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Shengzhou Liu 提交于
We use dynamical mtdparts partition instead of directly puting mtd partitions nodes in device tree. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Shengzhou Liu 提交于
We use dynamical mtdparts partition instead of directly puting mtd partitions nodes in device tree. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 vijay rai 提交于
T1040RDB, T1042RDB header files are very similar so merged into new header file T104xRDB. T104xRDB header file can support both T1040RDB and T1042RDB_PI header. Patch makes following changes -Update Boards.cfg file for T1040RDB and T1042RDB_PI -Add new T104xRDB header file -Delete T1040RDB, T1042RDB_PI header file Signed-off-by: NVijay Rai <vijay.rai@freescale.com> Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Prabhakar Kushwaha 提交于
Fix following compile warnings fsl_esdhc_spl.c: In function 'mmc_boot': fsl_esdhc_spl.c:35:10: warning: unused variable 'byte_num' [-Wunused-variable] fsl_esdhc_spl.c:35:7: warning: unused variable 'i' [-Wunused-variable] fsl_esdhc_spl.c:34:8: warning: unused variable 'val' [-Wunused-variable] fsl_esdhc_spl.c:33:6: warning: unused variable 'blklen' [-Wunused-variable] fsl_esdhc_spl.c:105:7: warning: 'tmp_buf' may be used uninitialized in this function [-Wuninitialized] Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 York Sun 提交于
Erratum A007212 for DDR is about a runaway condition for DDR PLL oscilliator. Please refer to erratum document for detail. For this workaround to work, DDR PLL needs to be disabled in RCW. However, u-boot needs to know the expected PLL ratio. We put the ratio in a reserved field RCW[18:23]. U-boot will skip this workaround if DDR PLL ratio is set, or the reserved field is not set. Workaround for erratum A007212 applies to selected versions of B4/T4 SoCs. It is safe to apply the workaround to all versions. It is helpful for upgrading SoC without changing u-boot. In case DDR PLL is disabled by RCW (part of the erratum workaround), we need this u-boot workround to bring up DDR clock. Signed-off-by: NYork Sun <yorksun@freescale.com>
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由 Shengzhou Liu 提交于
NOR flash is on CS1 instead of CS2 when NAND boot. So correct NOR chip selection to CS1 from CS2. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Nikhil Badola 提交于
Put a delay of 5 millisecond after reset so that ULPI phy gets enough time to come out of reset. Erratum A007075 applies to following SOCs and their variants, if any P1010 rev 1.0 B4860 rev 1.0, 2.0 P4080 rev 2.0, 3.0 Signed-off-by: NNikhil Badola <nikhil.badola@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 York Sun 提交于
T1040QDS_D4 is a variant of T1040QDS, with additional circuit to support DDR4 memory. Tested with MTA9ASF51272AZ-2G1AYESZG. Signed-off-by: NYork Sun <yorksun@freescale.com>
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由 York Sun 提交于
Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register calculation and programming. Signed-off-by: NYork Sun <yorksun@freescale.com>
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由 Scott Wood 提交于
The value written to L2CSR1 didn't match the value written to the device tree. Signed-off-by: NScott Wood <scottwood@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Codrin Ciubotariu 提交于
In the current Datasheet for VSC8514 there is a mistake, saying that the PHY id is 0x70570. The real value in the identifier registers is 0x70670. Linux PHY driver uses 0x70670 also. Signed-off-by: NCodrin Ciubotariu <codrin.ciubotariu@freescale.com> Cc: York Sun <yorksun@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 York Sun 提交于
For fsl-lsch3 NOR flash boot, IFC CS0 needs to be binded with address within 32-bit at fist. After u-boot relocates to DDR, CS0 can be binded to higher address to support large space. Signed-off-by: NYork Sun <yorksun@freescale.com> CC: Prabhakar Kushwaha <prabhakar@freescale.com>
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由 Prabhakar Kushwaha 提交于
The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher than 2.5 MHZ. It violates the IEEE specs. So Slow MDC clock to comply IEEE specs Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Zhao Qiang 提交于
add CONFIG_QE, CONFIG_U_QE and CONFIG_SYS_QE_FW_ADDR into "include/configs/T1040RDB.h" Signed-off-by: NZhao Qiang <B45475@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Zhao Qiang 提交于
Modify code to adapt to both u-qe and qe. U_QE is a kind of cutted QE. the differences between U_QE and QE 1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs. 2. IMMR: have different immr base addr. 3. iopin: U_QE doesn't need to config iopin. Signed-off-by: NZhao Qiang <B45475@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Zhao Qiang 提交于
CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address. Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address, and CONFIG_SYS_QE_FW_ADDR for QE microcode address. Signed-off-by: NZhao Qiang <B45475@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Aneesh Bansal 提交于
Secure Boot Target is added for T1040QDS and T1040RDB Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T1040QDS and CONFIG_T1040RDB Signed-off-by: NGaurav Rana <gaurav.rana@freescale.com> Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Aneesh Bansal 提交于
Secure Boot Target is added for T2080QDS Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T2080QDS. Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Aneesh Bansal 提交于
Secure Boot Target is added for T4240QDS and T4160QDS Changes: For Secure boot, CPC is configured as SRAM and used as house keeping area which needs to be disabled. So CONFIG_SYS_CPC_REINIT_F is defined for CONFIG_T4240QDS. Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Aneesh Bansal 提交于
Changes: 1. L2 cache is being invalidated by Boot ROM code for e6500 core. So removing the invalidation from start.S 2. Clear the LAW and corresponding configuration for CPC. Boot ROM code uses it as hosekeeping area. 3. For Secure boot, CPC is configured as SRAM and used as house keeping area. This configuration is to be disabled once in uboot. Earlier this disabling of CPC as SRAM was happening in cpu_init_r. As a result cache invalidation function was getting skipped in case CPC is configured as SRAM.This was causing random crashes. Signed-off-by: NRuchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Aneesh Bansal 提交于
In case of secure boot from NAND, the DDR is initialized by the BootROM using the config words (CF_WORDS) in the CF_HEADER and u-boot image is copied from NAND to DDR by the BootROM. So, CONFIG_SYS_RAMBOOT has been defined for Secure Boot from NAND Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Aneesh Bansal 提交于
Add NOR, SPI and SD secure boot targets for BSC9132QDS. Changes: - Debug TLB entry is not required for Secure Boot Target. Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Aneesh Bansal 提交于
ISBC creates a LAW 0 entry for non PBL platforms, which is not disabled before transferring the control to uboot. The LAW 0 entry has to be disabled. Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Aneesh Bansal 提交于
The workaround for IFC errata A003399 was not enabled in case of secure boot. So, secure boot from NOR was not working. Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Aneesh Bansal 提交于
In case of secure boot from NAND, the DDR is initialized by the BootROM using the config words (CF_WORDS) in the CF_HEADER and u-boot image is copied from NAND to DDR by the BootROM. So, CONFIG_SYS_RAMBOOT has been defined for Secure Boot from NAND. Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Nikhil Badola 提交于
Set correct phy_type value for second USB controller. This is required for supporting SOCs having 2 USB controllers working simultaneously, one with UTMI phy and other with ULPI phy Signed-off-by: NNikhil Badola <B46172@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alexander Graf 提交于
For KVM we have a special PV machine type called "ppce500". This machine is inspired by the MPC8544DS board, but implements a lot less features than that one. It also provides more PCI slots and is supposed to be enumerated by device tree only. This patch adds support for the generic ppce500 machine and tries to rely solely on device tree for device enumeration. Signed-off-by: NAlexander Graf <agraf@suse.de> Acked-by: NScott Wood <scottwood@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alexander Graf 提交于
We want to be able to directly execute the ELF binary without going through the u-boot.bin one. To know where we have to start executing this ELF binary we have to tell the linker where our entry point is. Signed-off-by: NAlexander Graf <agraf@suse.de> Acked-by: NScott Wood <scottwood@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alexander Graf 提交于
The DDR mapping function really is just a generic virtual -> physical mapping function. Generalize it so it can support any virtual starting offset and IO maps just the same. Signed-off-by: NAlexander Graf <agraf@suse.de> Acked-by: NScott Wood <scottwood@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alexander Graf 提交于
There is no need to set IVORs to anything but their default values, so let's leave them where they are. Suggested-by: NScott Wood <scottwood@freescale.com> Signed-off-by: NAlexander Graf <agraf@suse.de> Acked-by: NScott Wood <scottwood@freescale.com> [York Sun: Add back $(obj)start.S section in mpc8572ds/Makefile] Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alexander Graf 提交于
This patch adds a helper function that can be used to interpret most "ranges" properties in the device tree. It reads the n'th range out of a "ranges" array and returns the node's virtual address of the range, the physical address that range starts at and the size of the range. Signed-off-by: NAlexander Graf <agraf@suse.de> Acked-by: NScott Wood <scottwood@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alexander Graf 提交于
We already have a nice helper to give us a property cell value with default fall back from a path. Split that into two helpers - one for the old path based lookup and one to give us a value based on a node offset. Signed-off-by: NAlexander Graf <agraf@suse.de> Acked-by: NScott Wood <scottwood@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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- 19 4月, 2014 4 次提交
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由 Tom Rini 提交于
In 6e7b9f4f some of the debug prints for AES code moved into the generic code, so we remove these additional calls. Signed-off-by: NTom Rini <trini@ti.com> Acked-by: NTom Warren <twarren@nvidia.com>
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由 Stephen Warren 提交于
Tegra's crypto.c uses apply_cbc_chain_data() to sign the warm restart code. This function was recently moved into the core aes.c and made static, which prevents the Tegra code from compiling. Make it public again to avoid the compile errors: arch/arm/cpu/tegra20-common/crypto.c: In function ‘sign_object’: arch/arm/cpu/tegra20-common/crypto.c:74:3: warning: implicit declaration of function ‘apply_cbc_chain_data’ [-Wimplicit-function-declaration] arch/arm/cpu/built-in.o: In function `sign_object': .../arch/arm/cpu/tegra20-common/crypto.c:74: undefined reference to `apply_cbc_chain_data' .../arch/arm/cpu/tegra20-common/crypto.c:78: undefined reference to `apply_cbc_chain_data' Fixes: 6e7b9f4f ("aes: Move the AES-128-CBC encryption function to common code") Signed-off-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Acked-by: NMarek Vasut <marex@denx.de>
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由 Jon Loeliger 提交于
Prior to this patch, the top-level linker script u-boot.lds used a simple $(call if_changed) check when generated. That mechanism misses cases where a possible include file change induces a change in the u-boot.lds too. This patch converts it to a stronger check using ($call filechk) that will also notice differences in file contents and will catch changes due to pre-processing as well. Signed-off-by: NJon Loeliger <jon.loeliger@oracle.com>
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由 Daniel Schwierzeck 提交于
Add an option to specify the output directory to override the default path '../'. This is useful for building in a ramdisk. Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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