- 23 9月, 2018 12 次提交
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由 Stefan Roese 提交于
The Gardena Smart-Gateway boards have a MT7688 SoC with 128 MiB of RAM and 8 MiB of flash (SPI NOR) and additional 128MiB SPI NAND storage. This patch also includes 2 targets. One is the target that can be programmed into the SPI NOR flash and a 2nd target "xxx-ram" is added to support loading and booting via an already running U-Boot version. This allows easy development and testing without the need to flash the image each time. Signed-off-by: NStefan Roese <sr@denx.de> [fixed and regenerated defconfig files] Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
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由 Stefan Roese 提交于
The LinkIt Smart 7688 modules have a MT7688 SoC with 128 MiB of RAM and 32 MiB of flash (SPI NOR). This patch also includes 2 targets. One is the target that can be programmed into the SPI NOR flash and a 2nd target "xxx-ram" is added to support loading and booting via an already running U-Boot version. This allows easy development and testing without the need to flash the image each time. Signed-off-by: NStefan Roese <sr@denx.de> [fixed and regenerated defconfig files] Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
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由 Stefan Roese 提交于
This patch adds basic support for the MediaTek MT7620/88 SoCs. Parts of the code is copied from the MediaTek GitHub repository: https://github.com/MediaTek-Labs/linkit-smart-uboot.git The mt7628a.dtsi file is imported from Linux v4.17. Support for the LinkIt Smart 7688 module and the Gardena Smart Gateway both based on the MT7688 will be added in further patches. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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由 Stefan Roese 提交于
This is needed for the UBIFS support. The file is a copy of arch/xtensa/include/asm/atomic.h Signed-off-by: NStefan Roese <sr@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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由 Daniel Schwierzeck 提交于
Caches should be configured to mode CONF_CM_CACHABLE_NONCOHERENT (or CONF_CM_CACHABLE_COW when a CM is available). There is no need to make this configurable. Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
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由 Daniel Schwierzeck 提交于
The index base address used for the cache initialisation is currently hard-coded to CKSEG0. Make this value configurable if a MIPS system needs to have a different address (e.g. in SRAM or ScratchPad RAM). Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
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由 Daniel Schwierzeck 提交于
Changing the Cache Coherency Algorithm (CCA) for kernel mode requires executing from KSEG1. Thus do a jump from KSEG0 to KSEG1 before changing the CCA mode. Jump back to KSEG0 afterwards. Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
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由 Daniel Schwierzeck 提交于
Those functions are not needed during cache init and can be implemented in C. Only support the safe disabling of caches when this is required for booting an OS. Reenabling caches is much harder to implement if an optional coherency manager must be supported. As there is no real use-case anyway, dcache_enable is implemented with an error message. Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
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由 Daniel Schwierzeck 提交于
Some MIPS systems store some board-specific boot configuration in the U-Boot binary at offset 0x10. This is used by Malta boards and by Lantiq/Intel SoC's when booting from parallel NOR flash. Convert the hard-coded values to Kconfig options to remove such board-specific stuff out of the generic start.S code. This also deprecates the config option CONFIG_SYS_XWAY_EBU_BOOTCFG. Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
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由 Philippe Reynes 提交于
Signed-off-by: NPhilippe Reynes <philippe.reynes@softathome.com>
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由 Philippe Reynes 提交于
Add pinctrl node and related syscon node for broadcom bcm6838 SoC. Signed-off-by: NPhilippe Reynes <philippe.reynes@softathome.com>
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由 Philippe Reynes 提交于
Add pinctrl support for broadcom bcm6838 SoC. Signed-off-by: NPhilippe Reynes <philippe.reynes@softathome.com>
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- 20 9月, 2018 2 次提交
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git://git.denx.de/u-boot-marvell由 Tom Rini 提交于
- Multiples updates to the turris boards / platform - Changes / enhancements to the Marvell PHY drivers, mainly to support the turris platform - Many fixes and enhancements to the pxa3xx NAND driver - Fixes for the UART boot mode in kwboot - Misc minor changes to other 32bit and 64bit boards
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- 19 9月, 2018 26 次提交
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由 Baruch Siach 提交于
The Clearfog SOM can optionally have eMMC installed. Enable support for eMMC boot partitions by default. Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Rabeeh Khoury 提交于
This patch adds support to Armada 7k/8k comphy RX/TX lane swap. The 'phy-invert' DT property defines the inverted signals. Signed-off-by: NRabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Konstantin Porotchkin 提交于
Exclude mvebu commands from SPL builds Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Konstantin Porotchkin 提交于
Add definitions for CONFIG_ENV_SPI_BUS and CONFIG_ENV_SPI_CS to Armada-388-GP board configuration Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Konstantin Porotchkin 提交于
For some reason the spi_flash_probe_bus_cs() is called inside the setup_flash_device() with zero values in place of configurated SPI flash mode and maximum flash speed. This code causes HALT error during startup environment relocation on some platforms - namely Armada-38x-GP board. Fix the function call by replacing zeros with the appropriate values - CONFIG_ENV_SPI_MAX_HZ and CONFIG_ENV_SPI_MODE. Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
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由 David Sniatkiwicz 提交于
add delay before processing the status flags in pxa3xx_nand_irq(). Signed-off-by: NDavid Sniatkiwicz <davidsn@marvell.com> Reviewed-by: NIgal Liberman <igall@marvell.com> Reviewed-by: NKostya Porotchkin <kostap@marvell.com> c: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Konstantin Porotchkin 提交于
Add support for NAND chips with 8KB page, 4 and 8 bit ECC (ONFI). Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Reviewed-by: NOfer Heifetz <oferh@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Konstantin Porotchkin 提交于
Add comments with timing parameter names and some details about nand layout fileds. Remove unneeded definition. Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Reviewed-by: NIgal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Konstantin Porotchkin 提交于
Replace the hardcoded value of page chink with value that depends on flash page size and ECC strength. This fixes nand access errors for 2K page flashes with 8-bit ECC. Move the initial flash commannd function assignment past the ECC structures initialization for eliminating usage of hardcoded page chunk size value. Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Reviewed-by: NIgal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Konstantin Porotchkin 提交于
Add timings and device ID for Toshiba TC58NVG1S3HTA00 flash Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Reviewed-by: NIgal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Victor Axelrod 提交于
Add support for 2KB page 8-bit ECC strength flash layout Signed-off-by: NVictor Axelrod <victora@marvell.com> Reviewed-by: NIgal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Boris Brezillon 提交于
In the current driver, OOB bytes are accessed in raw mode, and when a page access is done with NDCR_SPARE_EN set and NDCR_ECC_EN cleared, the driver must read the whole spare area (64 bytes in case of a 2k page, 16 bytes for a 512 page). The driver was only reading the free OOB bytes, which was leaving some unread data in the FIFO and was somehow leading to a timeout. We could patch the driver to read ->spare_size + ->ecc_size instead of just ->spare_size when READOOB is requested, but we'd better make in-band and OOB accesses consistent. Since the driver is always accessing in-band data in non-raw mode (with the ECC engine enabled), we should also access OOB data in this mode. That's particularly useful when using the BCH engine because in this mode the free OOB bytes are also ECC protected. Fixes: 43bcfd2bb24a ("mtd: nand: pxa3xx: Add driver-specific ECC BCH support") Cc: stable@vger.kernel.org Reported-by: NSean Nyekjær <sean.nyekjaer@prevas.dk> Tested-by: NWilly Tarreau <w@1wt.eu> Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com> Acked-by: NEzequiel Garcia <ezequiel@vanguardiasur.com.ar> Tested-by: NSean Nyekjaer <sean.nyekjaer@prevas.dk> Acked-by: NRobert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: NRichard Weinberger <richard@nod.at> Signed-off-by: NOfer Heifetz <oferh@marvell.com> Reviewed-by: NIgal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ofer Heifetz 提交于
This commit is needed to properly support the 8-bits ECC configuration with 4KB pages. When pages larger than 2 KB are used on platforms using the PXA3xx NAND controller, the reading/programming operations need to be split in chunks of 2 KBs or less because the controller FIFO is limited to about 2 KB (i.e a bit more than 2 KB to accommodate OOB data). Due to this requirement, the data layout on NAND is a bit strange, with ECC interleaved with data, at the end of each chunk. When a 4-bits ECC configuration is used with 4 KB pages, the physical data layout on the NAND looks like this: | 2048 data | 32 spare | 30 ECC | 2048 data | 32 spare | 30 ECC | So the data chunks have an equal size, 2080 bytes for each chunk, which the driver supports properly. When a 8-bits ECC configuration is used with 4KB pages, the physical data layout on the NAND looks like this: | 1024 data | 30 ECC | 1024 data | 30 ECC | 1024 data | 30 ECC | 1024 data | 30 ECC | 64 spare | 30 ECC | So, the spare area is stored in its own chunk, which has a different size than the other chunks. Since OOB is not used by UBIFS, the initial implementation of the driver has chosen to not support reading this additional "spare" chunk of data. Unfortunately, Marvell has chosen to store the BBT signature in the OOB area. Therefore, if the driver doesn't read this spare area, Linux has no way of finding the BBT. It thinks there is no BBT, and rewrites one, which U-Boot does not recognize, causing compatibility problems between the bootloader and the kernel in terms of NAND usage. To fix this, this commit implements the support for reading a partial last chunk. This support is currently only useful for the case of 8 bits ECC with 4 KB pages, but it will be useful in the future to enable other configurations such as 12 bits and 16 bits ECC with 4 KB pages, or 8 bits ECC with 8 KB pages, etc. All those configurations have a "last" chunk that doesn't have the same size as the other chunks. In order to implement reading of the last chunk, this commit: - Adds a number of new fields to the pxa3xx_nand_info to describe how many full chunks and how many chunks we have, the size of full chunks and partial chunks, both in terms of data area and spare area. - Fills in the step_chunk_size and step_spare_size variables to describe how much data and spare should be read/written for the current read/program step. - Reworks the state machine to accommodate doing the additional read or program step when a last partial chunk is used. This commit is taken from Linux: 'commit c2cdace755b' ("mtd: nand: pxa3xx_nand: add support for partial chunks") Signed-off-by: NChris Packham <judge.packham@gmail.com> Signed-off-by: NOfer Heifetz <oferh@marvell.com> Reviewed-by: NIgal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ofer Heifetz 提交于
This commit simplifies the initial configuration performed by pxa3xx_nand_scan. No functionality change is intended. This commit is taken from Linux: 'commit 154f50fbde53' ("mtd: pxa3xx_nand: Simplify pxa3xx_nand_scan") Signed-off-by: NChris Packham <judge.packham@gmail.com> Signed-off-by: NOfer Heifetz <oferh@marvell.com> Reviewed-by: NIgal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ofer Heifetz 提交于
The Data Flash Control Register (NDCR) contains two types of parameters: those that are needed for device identification, and those that can only be set after device identification. Therefore, the driver can't set them all at once and instead needs to configure the first group before nand_scan_ident() and the second group later. Let's split pxa3xx_nand_config in two halves, and set the parameters that depend on the device geometry once this is known. This commit is taken from Linux: 'commit 66e8e47eae65' ("mtd: pxa3xx_nand: Fix initial controller configuration") Signed-off-by: NChris Packham <judge.packham@gmail.com> Signed-off-by: NOfer Heifetz <oferh@marvell.com> Reviewed-by: NIgal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ofer Heifetz 提交于
The chunk size represents the size of the data chunks, which is used by the controllers that allow to split transferred data. However, the initial chunk size is used in a non-split way, during device identification. Therefore, it must be large enough for all the NAND commands issued during device identification. This includes NAND_CMD_PARAM which was recently changed to transfer up to 2048 bytes (for the redundant parameter pages). Thus, the initial chunk size should be 2048 as well. On Armada 370/XP platforms (NFCv2) booted without the keep-config devicetree property, this commit fixes a timeout on the NAND_CMD_PARAM command: [..] pxa3xx-nand f10d0000.nand: This platform can't do DMA on this device pxa3xx-nand f10d0000.nand: Wait time out!!! nand: device found, Manufacturer ID: 0x2c, Chip ID: 0x38 nand: Micron MT29F8G08ABABAWP nand: 1024 MiB, SLC, erase size: 512 KiB, page size: 4096, OOB size: 224 This commit is taken from Linux: 'commit c7f00c29aa8' ("mtd: pxa3xx_nand: Increase the initial chunk size") Signed-off-by: NChris Packham <judge.packham@gmail.com> Signed-off-by: NOfer Heifetz <oferh@marvell.com> Reviewed-by: NIgal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ofer Heifetz 提交于
The read ID count should be made as large as the maximum READ_ID size, so there's no need to have dynamic size. This commit sets the hardware maximum read ID count, which should be more than enough on all cases. Also, we get rid of the read_id_bytes, and use a macro instead. This commit is taken from Linux: 'commit b226eca2088' ("nand: pxa3xx: Increase READ_ID buffer and make the size static") Signed-off-by: NChris Packham <judge.packham@gmail.com> Signed-off-by: NOfer Heifetz <oferh@marvell.com> Reviewed-by: NIgal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ofer Heifetz 提交于
When 2 commands are submitted in a row, and the second is very quick, the completion of the second command might never come. This happens especially if the second command is quick, such as a status read after an erase This patch is taken from Linux: 'commit 21fc0ef9652f' ("mtd: nand: pxa3xx-nand: fix random command timeouts") Signed-off-by: NChris Packham <judge.packham@gmail.com> Signed-off-by: NOfer Heifetz <oferh@marvell.com> Reviewed-by: NIgal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ofer Heifetz 提交于
When the nand is first probe, and upon the first command start, the status bits should be cleared before the interrupts are unmasked. This commit is taken from Linux: 'commit 0b14392db2e' ("mtd: nand: pxa3xx_nand: fix early spurious interrupt") Signed-off-by: NChris Packham <judge.packham@gmail.com> Signed-off-by: NOfer Heifetz <oferh@marvell.com> Reviewed-by: NIgal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ofer Heifetz 提交于
Since the pxa3xx_nand driver was added there has been a discrepancy in pxa3xx_nand_set_sdr_timing() around the setting of tWP_min and tRP_min. This brings us into line with the current Linux code. Signed-off-by: NChris Packham <judge.packham@gmail.com> Signed-off-by: NOfer Heifetz <oferh@marvell.com> Reviewed-by: NIgal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ofer Heifetz 提交于
Don't store struct mtd_info in struct pxa3xx_nand_host. Instead use the one that is already part of struct nand_chip. This brings us in line with current U-boot and Linux conventions. Signed-off-by: NChris Packham <judge.packham@gmail.com> Signed-off-by: NOfer Heifetz <oferh@marvell.com> Reviewed-by: NIgal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ofer Heifetz 提交于
The initial buffer is used for the initial commands used to detect a flash device (STATUS, READID and PARAM). ONFI param page is 256 bytes, and there are three redundant copies to be read. JEDEC param page is 512 bytes, and there are also three redundant copies to be read. Hence this buffer should be at least 512 x 3. This commits rounds the buffer size to 2048. This commit is taken from Linux: 'commit c16340973fcb64614' ("nand: pxa3xx: Increase initial buffer size") Signed-off-by: NChris Packham <judge.packham@gmail.com> Signed-off-by: NOfer Heifetz <oferh@marvell.com> Reviewed-by: NIgal Liberman <igall@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Marek Behún 提交于
If PCIe Mox module is connected we want to have PCIe node enabled in U-Boot's device tree. Signed-off-by: NMarek Behun <marek.behun@nic.cz> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Baruch Siach 提交于
Commit 61dccf73 (dts: mvebu: a80x0: Enable SD/eMMC interfaces) added a redundant DT node for SD card slot. Drop it. Cc: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Marek Behún 提交于
Remove smi_pins definition since it is already in armada-37xx.dtsi. Add assigned-clocks definitions to spi0. Signed-off-by: NMarek Behun <marek.behun@nic.cz> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Marek Behún 提交于
Enable the pci-aardvark driver in defconfig for Turris Mox and also enable the pci command. Signed-off-by: NMarek Behun <marek.behun@nic.cz> Signed-off-by: NStefan Roese <sr@denx.de>
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