When booting as a coreboot payload, we don't need write any
configuration tables as coreboot does that for us.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>

Instead of hiding each menu entries under "System tables" for EFI,
hide the main menu completely.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>

Some platforms may have >=4GiB memory, so we need make U-Boot report
such configuration correctly when booting as the coreboot payload.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>

Now that we have generic routine to calculate relocation address,
remove the x86 specific one which is now only used by coreboot.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>

coreboot has some extensions (type 6 & 16) to the E820 types.
When we detect this, mark it as E820_RESERVED.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>

Increase lib_sysinfo memrange entry number to 32 to sync with coreboot.
This allows a complete E820 table to be reported to the kernel, as on
some platforms (eg: Bayley Bay) having only 16 entires does not cover
all the memory ranges.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>

With recent EFI support, the entry point address of coreboot payload
was changed. Now we update the address to use _x86boot_start, which
is the same one for EFI.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>

commit 6497e37a "net: e1000: Support 64-bit physical address" causes
compiler warnings on 32-bit U-Boot build below.

drivers/net/e1000.c: In function 'e1000_configure_tx':
drivers/net/e1000.c:4982:2: warning: right shift count >= width of type [enabled by default]
drivers/net/e1000.c: In function 'e1000_configure_rx':
drivers/net/e1000.c:5126:2: warning: right shift count >= width of type [enabled by default]

This commit fixes the build warnings.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

This is useful once Andrew's PXA I2C driver gets merged.
Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>

Add optional LCD support. Note that depending on the toolchain used
one might have to drop some other features to stay within the 0x40000
size limit.
Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>

Add some more NOR flash details like size, bus width and lock/unlock
time outs.
Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>

Looks like the define CONFIG_SYS_LCD_PXA_NO_L_BIAS is not used anywhere
else throughout the U-Boot sources any more. Drop it.
Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>

Cleaning up order of include files by sorting them alphabetically
keeping in mind to leave common.h on top.
Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>

Cleaning up order of include files by sorting them alphabetically
keeping in mind to leave common.h on top.
Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>

Cleaning up order of include files by sorting them alphabetically
keeping in mind to leave common.h on top.
Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>

Cleaning up order of include files by sorting them alphabetically
keeping in mind to leave common.h on top.
Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>

Cleaning up order of include files by sorting them alphabetically
keeping in mind to leave common.h on top.
Signed-off-by: NMarcel Ziswiler <marcel@ziswiler.com>

This patch moves pxa to the common timer functions added in commit

  8dfafdde - Introduce common timer functions <Rob Herring>

The (removed) pxa timer code (specifically __udelay()) could deadlock at
the 32-bit boundary of get_ticks().  get_ticks() returned a 32-bit value
cast up to a 64-bit value.  If get_ticks() + tmo in __udelay() crossed
the 32-bit boundary, the while condition became unconditionally true and
locked the processor.  Rather than patch the specific pxa issues, simply
move everything over to the common code.
Signed-off-by: NAndrew Ruder <andrew.ruder@elecsyscorp.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsuiko.com>

Since commit 3ff46cc4 ("arm: relocate the exception vectors")
pxa does not boot anymore.

Add a specific relocate_vectors macro that skips the vector relocation,
as the pxa SoC does not provide RAM at the high vectors address
(0xFFFF0000), and (0x00000000) maps to ROM.

This allows pxa to boot again.

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: NAndrew Ruder <andrew.ruder@elecsyscorp.com>

Conflicts:
	configs/socfpga_arria5_defconfig
	configs/socfpga_cyclone5_defconfig
	configs/socfpga_socrates_defconfig

Merged these by hand and re-ran savedefconfig on them.
Signed-off-by: NTom Rini <trini@konsulko.com>

Pull out the ArriaV SoCDK clock config from ancient Altera U-Boot
"rel_socfpga_v2013.01.01_15.05.01_pr" and implant those values into
mainline to get a booting ArriaV SoCDK.
Signed-off-by: NMarek Vasut <marex@denx.de>

Synchronise the config options with Cyclone V SoCDK and other boards.
This enables ethernet on the ArriaV SoCDK.
Signed-off-by: NMarek Vasut <marex@denx.de>

Add the missing DT nodes, so that ArriaV SoCDK can boot from SD
card. The SD card must be in slot J5 and BSEL must be 0x5.
Signed-off-by: NMarek Vasut <marex@denx.de>

Repair the maintainer entries so they match the current state of code.
Signed-off-by: NMarek Vasut <marex@denx.de>

Enable the DWAPB GPIO driver for SoCFPGA Cyclone V and Arria V.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>

Add "bank-name" property to each GPIO bank to give it unique name.
The approach here is exactly the same as with the "regulator-name"
property for regulators.
Signed-off-by: NMarek Vasut <marex@denx.de>

Add driver for the DesignWare APB GPIO IP block.
This driver is DM capable and probes from DT.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>

Now that we're actually converting the QTS-generated header files,
we can even adjust their data types. A good candidate for this is
the pinmux table, where each entry can have value in the range of
0..3, but each element is declared as unsigned long. By changing
the type to u8, we can save over 600 Bytes from the SPL, so do it.
This patch also constifies the array.
Signed-off-by: NMarek Vasut <marex@denx.de>

Signed-off-by: NMarek Vasut <marex@denx.de>

Add script which loads the QTS-generated sources and headers and converts
them into sensible format which can be used with much more easy in mainline
U-Boot. The script also filters out macros which makes no sense anymore, so
they don't pollute namespace and waste space.
Signed-off-by: NMarek Vasut <marex@denx.de>

Just remove the ArriaV specific parts from the CycloneV SoCDK board
and they are no longer needed now.
Signed-off-by: NMarek Vasut <marex@denx.de>

Just remove the CycloneV specific parts from the ArriaV SoCDK board
and they are no longer needed now.
Signed-off-by: NMarek Vasut <marex@denx.de>

The board/altera/socfpga directory is not a generic SoCFPGA machine
anymore, but instead it represents the Altera SoCDK board. To make
matters more complicated, it represents both CycloneV and ArriaV
variant.

On the other hand, nowadays, the content of this board directory is
mostly comprised of QTS-generated header files, while all the generic
code is in arch/arm/mach-socfpga already.

Thus, this patch splits the board/altera/socfpga into a separate
board directory for ArriaV SoCDK and CycloneV SoCDK, so that each
can be populated with the correct QTS-generated header files for
that particular board.
Signed-off-by: NMarek Vasut <marex@denx.de>

The CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5
selected both a board and a CPU. This is not correct as these macros
are supposed to select only board.

All would be good, if QTS-generated header files didn't check for
these macros exactly to determine if the platform is Cyclone V or
Arria V. Thus, for the sake of compatibility with not well fleshed
out header file generator, this patch makes these two macros into
a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK
and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the
previous stub config option.

The result is that compatibility with QTS is preserved and the new
CONFIG_TARGET_* select actual target boards.
Signed-off-by: NMarek Vasut <marex@denx.de>

Move the wrappers for QTS-generated files into platform directory
out of the board directory. The trick here is to add -I to CFLAGS
such that it points to the board directory in source tree and thus
the qts/ directory there is still reachable.
Signed-off-by: NMarek Vasut <marex@denx.de>

The GMAC which is enabled is purely board property, so do not enable
arbitrary GMAC in DT include files. Same goes for PHY mode, which is
again a board property. The CycloneV SoCDK does this correctly, but
SoCrates doesn't. This bug never manifested itself though, since all
the boards ever used the GMAC1 . This bug manifests itself only on
boards that utilise GMAC0.
Signed-off-by: NMarek Vasut <marex@denx.de>

The socfpga_cyclone5.dtsi has an mmc0 node, socrates has mmc node.
This makes aliases not very usable, so make everything into mmc0.
Moreover, zap the useless mmc alias while at this.
Signed-off-by: NMarek Vasut <marex@denx.de>