'-elf' appears twice in the toolchain priority_list.
The second one is rudundant.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: NSimon Glass <sjg@chromium.org>

Toolchains.__init__ is expected to display a warning message
when the [toolchain] section is missing from ~/.buildman file.
But it never works.
In that case, instead, buildmain fails with an error message
which is difficult to understand:

  Traceback (most recent call last):
    File "tools/buildman/buildman", line 126, in <module>
      control.DoBuildman(options, args)
    File "/home/foo/u-boot/tools/buildman/control.py", line 78, in DoBuildman
      toolchains = toolchain.Toolchains()
    File "/home/foo/u-boot/tools/buildman/toolchain.py", line 106, in __init__
    config_fname)
  NameError: global name 'config_fname' is not defined
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: NSimon Glass <sjg@chromium.org>

Now MIPS supports 'generic board' feature.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: NSimon Glass <sjg@chromium.org>

When patman applies the patches it checks out a new branch, uses 'git am'
to apply the patches one by one, and then tries to go back to the old
branch. If you try this when the branch is 'undefined', this doesn't work
as patman cannot restore the correct branch after applying the patches.
It seems that 'undefined' is created by git and is persistent after it is
created, so that you can end up on quite an old branch.

Add a check for the 'undefined' branch to avoid this.
Reported-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: NSimon Glass <sjg@chromium.org>

To move the arch common function away from board folder to
arch/arm/cpu/armv7/socfpga folder. Its to avoid code duplication
for other non Altera dev kit which is using socfpga device.
Signed-off-by: NChin Liang See <clsee@altera.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Acked-by: NDetlev Zundel <dzu@denx.de>

Turn on generic board for the integrators, as per the request in
the startup message. Everything just works, tested on the
Integrator/AP and Integrator/CP.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NSimon Glass <sjg@chromium.org>

Serial port, SD card, and LCD all work.
Signed-off-by: NStephen Warren <swarren@wwwdotorg.org>
Acked-by: NSimon Glass <sjg@chromium.org>

Signed-off-by: NChristian Riesch <christian.riesch@omicron.at>

Fix following compilation error when CONFIG_ARM64 is defined

Error: unknown or missing system register name at operand 2
-- `mrs x0,daifmsr daifset,#3'
Signed-off-by: NShaibal.Dutta <shaibal.dutta@broadcom.com>
Signed-off-by: NDarwin Rambo <drambo@broadcom.com>
Reviewed-by: NDarwin Rambo <drambo@broadcom.com>

Enable 'generic board init' for H2200 palmtop.
Signed-off-by: NLukasz Dalek <luk0104@gmail.com>
Acked-by: NMarek Vasut <marex@denx.de>

cc: Tom Rini <trini@ti.com>
Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl>

Run tools/reformat.py -i -d '-' -s 8
to reorder boards as header comments suggest

Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: NChin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Wolfgang Denk <wd@denx.de>
CC: Pavel Machek <pavel@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>

To enable the DesignWare watchdog support at SOCFPGA
Cyclone V dev kit.
Signed-off-by: NChin Liang See <clsee@altera.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>

To add the DesignWare watchdog driver support. It required
information such as register base address and clock info from
configuration header file  within include/configs folder.
Signed-off-by: NChin Liang See <clsee@altera.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@ti.com>

This patch returns back support for old ep93xx processors family
Signed-off-by: NSergey Kostanbaev <sergey.kostanbaev@gmail.com>
Cc: albert.u.boot@aribaud.net

In current gpio_set_value() implementation, it always sets the gpio control bit
no matter the value argument is 0 or 1. Thus the GPIOs never set to low.
This patch fixes this bug.

The address bus is used as a mask on read/write operations, so that independent
software drivers can set their GPIO bits without affecting any other pins in a
single write operation. Thus we don't need a read-modify-write to update the
register.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Acked-by: NStefan Roese <sr@denx.de>
Reviewed-by: NVipin Kumar <vipin.kumar@st.com>
Reviewed-by: NMichael Trimarchi <michael@amarulasolutions.com>

This is not only more readable but also prevents a warning
about a missing prototype. The prototypes which are actually
missing are added.

cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: NTom Rini <trini@ti.com>

LS2085A is an ARMv8 implementation. This adds board support for emulator
and simulator:
  Two DDR controllers
  UART2 is used as the console
  IFC timing is tightened for speedy booting
  Support DDR3 and DDR4 as separated targets
  Management Complex (MC) is enabled
  Support for GIC 500 (based on GICv3 arch)
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NArnab Basu <arnab.basu@freescale.com>
Signed-off-by: NJ. German Rivera <German.Rivera@freescale.com>
Signed-off-by: NBhupesh Sharma <bhupesh.sharma@freescale.com>

Adding support to load and start the Layerscape Management Complex (MC)
firmware. First, the MC GCR register is set to 0 to reset all cores. MC
firmware and DPL images are copied from their location in NOR flash to
DDR. MC registers are updated with the location of these images.
Deasserting the reset bit of MC GCR register releases core 0 to run.
Core 1 will be released by MC firmware. Stop bits are not touched for
this step. U-boot waits for MC until it boots up. In case of a failure,
device tree is updated accordingly. The MC firmware image uses FIT format.
Signed-off-by: NJ. German Rivera <German.Rivera@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NLijun Pan <Lijun.Pan@freescale.com>
Signed-off-by: NShruti Kanetkar <Shruti@Freescale.com>

Freescale LayerScape with Chassis Generation 3 is a set of SoCs with
ARMv8 cores and 3rd generation of Chassis. We use different MMU setup
to support memory map and cache attribute for these SoCs. MMU and cache
are enabled very early to bootst performance, especially for early
development on emulators. After u-boot relocates to DDR, a new MMU
table with QBMan cache access is created in DDR. SMMU pagesize is set
in SMMU_sACR register. Both DDR3 and DDR4 are supported.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NVarun Sethi <Varun.Sethi@freescale.com>
Signed-off-by: NArnab Basu <arnab.basu@freescale.com>

Make MMU function reusable. Platform code can setup its own MMU tables.
Signed-off-by: NYork Sun <yorksun@freescale.com>
CC: David Feng <fenghua@phytium.com.cn>

This is needed for accessing peripherals with 64-bit MMIO registers,
from ARMv8 processors.
Signed-off-by: NJ. German Rivera <German.Rivera@freescale.com>

The armv8 ARM Trusted Firmware (ATF) can be used to load various ATF
images and u-boot, and does this for virtual platforms by using
semihosting. This commit extends this idea by allowing u-boot to also
use semihosting to load the kernel/ramdisk/dtb. This eliminates the need
for a bootwrapper and produces a more realistic boot sequence with
virtual models.

Though the semihosting code is quite generic, support for armv7 in
fastmodel is less useful due to the wide range of available silicon
and the lack of a free armv7 fastmodel, so this change contains an
untested armv7 placeholder for the service trap opcode.

Please refer to doc/README.semihosting for a more detailed description
of semihosting and how it is used with the armv8 virtual platforms.
Signed-off-by: NDarwin Rambo <drambo@broadcom.com>
Cc: trini@ti.com
Cc: fenghua@phytium.com.cn
Cc: bhupesh.sharma@freescale.com

Since tegra_i2c_{read,write}'s debug() call dumps the chip address, dump
the address length (alen) too, so the address value can be correctly
interpreted.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NYen Lin <yelin@nvidia.com>

The Tegra I2C controller's TX FIFO contains 32-bit words. If the final
FIFO entry of a transaction contains fewer than 4 bytes, the driver
currently fills the unused FIFO bytes with uninitialized data. This can
be confusing when reading back the FIFO content for debugging purposes.

Solve this by explicitly initializing the variable containing FIFO data
before filling it (partially) with data. With this change,
send_recv_packets()'s loop's if (is_write) code mirrors the else (i.e.
read) branch.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NYen Lin <yelin@nvidia.com>

I2C read transactions are typically implemented as follows:

START(write) address REPEATED_START(read) data... STOP

However, Tegra's I2C driver currently implements reads as follows:

START(write) address STOP START(read) data... STOP

This sequence confuses at least the AS3722 PMIC on the Jetson TK1 board,
leading to corrupted read data in some cases. Fix the driver to chain
the transactions together using repeated starts to solve this.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NYen Lin <yelin@nvidia.com>

Signed-off-by: NTom Rini <trini@ti.com>

Almost all of ci_udc.c uses variable name "ep" for a struct usb_ep and
"ci_ep" for a struct ci_ep. This is nice and consistent, and helps people
know what type a variable is without searching for the declaration.
handle_ep_complete() doesn't do this, so fix it to be consistent.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

A UDC's alloc_request method should zero out the newly allocated request.
Ensure the Atmel driver does so. This issue was found by code inspection,
following the investigation of an intermittent issue with ci_udc, which
was tracked down to failing to zero out allocated requests following some
of my changes. All other UDC drivers already zero out requests in one
way or another.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

struct ci_req is a purely software structure, and needs no specific
memory alignment. Hence, allocate it with calloc() rather than
memalign(). The use of memalign() was left-over from when struct ci_req
was going to hold the aligned bounce buffer, but this is now dynamically
allocated.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

There's no need to store an array of QTD pointers in the controller.
Since the calculation is so simple, just have ci_get_qtd() perform it
at run-time, rather than pre-calculating everything.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

2 QTDs are allocated for each EP. The current allocation scheme aligns
the first QTD in each pair, but simply adds the struct size to calculate
the second QTD's address. This will result in a non-cache-aligned
addresss IF the system's ARCH_DMA_MINALIGN is not 32 bytes (i.e. the
size of struct ept_queue_item).

Similarly, the original ilist_ent_sz calculation aligned the value to
ARCH_DMA_MINALIGN but didn't take the USB HW's 32-byte alignment
requirement into account. This doesn't cause a practical issue unless
ARCH_DMA_MINALIGN < 32 (which I suspect is quite unlikely), but we may
as well fix the code to be explicit, so it's obviously completely
correct.

The new value of ILIST_ENT_SZ takes all alignment requirements into
account, so we can simplify ci_{flush,invalidate}_qtd() by simply using
that macro rather than calling roundup().

Similarly, the calculation of controller.items[i] can be simplified,
since each QTD is evenly spaced at its individual alignment requirement,
rather than each pair being aligned, and entries within the pair being
spaced apart only by structure size.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

This will allow functions other than ci_udc_probe() to make use of the
constants in a future change.

This in turn requires converting the const int variables to #defines,
since the initialization of one global const int can't depend on the
value of another const int; the compiler thinks it's non-constant if
that dependency exists.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Fix ci_ep_submit_next_request()'s ZLP transmission code to explicitly
call ci_get_qtd() to find the address of the other QTD to use. This
will allow us to correctly align each QTD individually in the future,
which may involve leaving a gap between the QTDs.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

ci_udc_probe() initializes a pair of QHs and QTDs for each EP. After
each pair has been initialized, the pair is cache-flushed. The
conversion from QH/QTD index [0..2*NUM_END_POINTS) to EP index
[0..NUM_ENDPOINTS] is incorrect; it simply subtracts 1 (which yields
the QH/QTD index of the first entry in the pair) rather than dividing
by two (which scales the range). Fix this.

On my system, this avoids cache debug prints due to requests to flush
unaligned ranges. This is caused because the flush calls happen before
the items[] array entries are initialized for all but EP0.
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Conflicts:
	boards.cfg

Conflict was trivial between goni maintainer change and
lager_nor removal.