The current 'cpld reset' will just write global_rst register
but couldn't switch to NOR boot if the board's switches are
for NAND/SD boot. So need to write rcw source registers for
NOR boot as well.
Signed-off-by: NGong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Mix usage of uint32_t and u32 fixed in favor of u32.
Signed-off-by: NVincent Siles <vincent.siles@provenrun.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

On the LS102x boards, in order to initialize the ICID values of
masters, the dev_stream_id array holds absolute offsets from the
base of SCFG.

In ls102xa_config_ssmu_stream_id, the base pointer is cast to
uint32_t * before adding the offset, leading to an invalid address.
Casting it to void * solves the issue.
Signed-off-by: NVincent Siles <vincent.siles@provenrun.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

As the issue about the stack will get corrupted when switching between
the early and final mmu tables is fixed by commit 70e21b06, the
workaround to flush dcache is unnecessary and should be removed.
Signed-off-by: NAlison Wang <alison.wang@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

As per new PHY framework, DPNI naming convetion is no more used.
Use new naming convention.
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Define CONFIG_FSL_CAAM for LS2080 which would enable
call to sec_init() during U-Boot.
Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

The address value and size value set for QSPI dts node "reg"
property have type of u64 on arm64.
Signed-off-by: NYuan Yao <yao.yuan@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

The S25FS-S family physical sectors may be configured as a hybrid
combination of eight 4-kB parameter sectors at the top or bottom
of the address space with all but one of the remaining sectors
being uniform size.
The default status of the flash is in this hybrid architecture.
The parameter sectors and the uniform sectors have different erase
commands.
This patch disable the hybrid sector architecture then the flash will
has uniform sector size and uniform erase command.
This configuration is temporary, the flash will revert to hybrid
architecture after power on reset.
Signed-off-by: NYuan Yao <yao.yuan@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

The flash type of LS2085AQDS QSPI is S25FS256S. It has special write
any device register command and read any device register command.
This patch enable support for those commands.
Signed-off-by: NYuan Yao <yao.yuan@nxp.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

QSPI controller automatic enable the chipselect signal according the
dest AMBA memory address. Now we distribute the AMBA memory zone
averagely to every chipselect slave device according chipselect
numbers got from dts node.
Signed-off-by: NYuan Yao <yao.yuan@nxp.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

The address value and size value get from dts "reg" property have
type of u64 on arm64. If we assign those values to "u32" variables,
driver can't work correctly. Converting the type of those variables
to fdt_xxx_t.
Signed-off-by: NYuan Yao <yao.yuan@nxp.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

For Qoriq PPC&ARM v7 platforms, the crypto node is being fixup'ed in
order to update the SEC internal version (aka SEC ERA). This patch
adds the same functionality to the ARMv8 SoCs.
Signed-off-by: NAlex Porosanu <alexandru.porosanu@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Update MAINTAINERS file for ls2080aqds and ls2080ardb platforms.
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Optimize DDR timing for good margins to support new Transcend
and Apacer DDR4 UDIMM besides current Micron UDIMM.

Verified 1333MT/s, 1600MT/s, 1866MT/s, 2133MT/s rate with
following UDIMM on LS2080ARDB.
 - Micron UDIMM: MTA18ASF1G72AZ-2G1A1Z
 - Apacer UDIMM: 78.C1GM4.AF10B
 - Transcend UDIMM: TS1GLH72V1H
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

The initial training for the DDRC may provide results that are not
optimized. The workaround provides better read timing margins.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Per the latest erratum document, update step 4 and step 8, only
DEBUG_29[21] is changed, all other bits should not be changed.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Barrier transactions from CCI400 need to be disabled till
the DDR is configured, otherwise it may lead to system hang.
The patch adds workaround to fix the erratum.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Signed-off-by: NTom Rini <trini@konsulko.com>

Reported-and-tested-by: NDennis Gilmore <dennis@ausil.us>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

update tbot documentation in U-Boot, as I just
merged the event system into tbots master
branch.
Signed-off-by: NHeiko Schocher <hs@denx.de>

test/py raises an error, if a board has not enabled bdi command

>           pytest.skip('bdinfo command not supported')
E           NameError: global name 'pytest' is not defined

import pytest in test/py/u_boot_utils.py fixes this.
Signed-off-by: NHeiko Schocher <hs@denx.de>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

Commit bfb33f0b ("sunxi: mctl_mem_matches: Add missing memory
barrier") broke compilation for the Pine64, as dram_helper.c now
includes <asm/armv7.h>, which does not compile on arm64.

Fix this by moving all barrier instructions into a separate header
file, which can easily be shared between arm and arm64.
Also extend the inline assembly to take the "sy" argument, which is
optional for ARMv7, but mandatory for v8.

This fixes compilation for 64-bit sunxi boards (Pine64).
Acked-by: NIan Campbell <ijc@hellion.org.uk>
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>

Update the pinmux and pll configuration for the Cyclone5 RevE or later devkit.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>

CONFIG_OF_LIBFDT needs to be selected to avoid the following
boot problem:

reading zImage
6346216 bytes read in 118 ms (51.3 MiB/s)
Booting from mmc ...
reading imx7d-warp.dtb
32593 bytes read in 11 ms (2.8 MiB/s)
Kernel image @ 0x80800000 [ 0x000000 - 0x60d5e8 ]
FDT and ATAGS support not compiled in - hanging
### ERROR ### Please RESET the board ###
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>

Reported by Coverity:
Logically dead code (DEADCODE)
dead_error_line: Execution cannot reach this statement:
(f_dfu->strings + --i).s = ....

If calloc failed, i is still 0 and no need to call free,
so discard the dead code.
Signed-off-by: NPeng Fan <van.freenix@gmail.com>
Cc: "Łukasz Majewski" <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>

When dfu_fill_entity fail, need to free dfu to avoid memory leak.

Reported by Coverity:
"
Resource leak (RESOURCE_LEAK)
leaked_storage: Variable dfu going out of scope leaks the storage
it points to.
"
Signed-off-by: NPeng Fan <van.freenix@gmail.com>
Cc: "Łukasz Majewski" <l.majewski@samsung.com>
Cc: Marek Vasut <marex@denx.de>

With patch c998da0d (usb: Change power-on / scanning timeout handling),
the USB scanning is started earlier and with a smaller timeout. This
resulted on SoCFPGA (using the DWC2 driver) in some USB sticks not
getting detected any more. This patch now adds a 1 second delay (in
the host mode only) to the DWC2 driver before the scanning is started.
With this delay, now all problematic USB keys are detected successfully
again. And there is no need any more to change the delay / timeout
in the common USB code (usb_hub.c).
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Marek Vasut <marex@denx.de>

The code shouldn't continue probing the port if get_port_status() failed.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Stephen Warren <swarren@nvidia.com>

The Kingston DT Ultimate USB 3.0 stick is sensitive to this first
Get Descriptor request and if the request is not in a separate
microframe, the stick refuses to operate. Add slight delay, which
is enough for one microframe to pass on any USB spec revision.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Stephen Warren <swarren@nvidia.com>

Some devices, like the SanDisk Cruzer Pop need some time to process
the Set Configuration request, so wait a little until they are ready.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Stephen Warren <swarren@nvidia.com>

Building without ethernet driver doesn't work. Fix it.
Signed-off-by: NAnatolij Gustschin <agust@denx.de>
Cc: Marek Vasut <marex@denx.de>

The indirect read code is a pile of nastiness. This patch replaces
the whole unmaintainable indirect read implementation with the one
from upcoming Linux CQSPI driver, which went through multiple rounds
of thorough review and testing. All the patch does is it plucks out
duplicate ad-hoc code distributed across the driver and replaces it
with more compact code doing exactly the same thing. There is no
speed change of the read operation.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Jagan Teki <jteki@openedev.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vignesh R <vigneshr@ti.com>

The indirect write code is buggy pile of nastiness which fails horribly
when the system runs fast enough to saturate the controller. The failure
results in some pages (256B) not being written to the flash. This can be
observed on systems which run with Dcache enabled and L2 cache enabled,
like the Altera SoCFPGA.

This patch replaces the whole unmaintainable indirect write implementation
with the one from upcoming Linux CQSPI driver, which went through multiple
rounds of thorough review and testing. While this makes the patch look
terrifying and violates all best-practices of software development, all
the patch does is it plucks out duplicate ad-hoc code distributed across
the driver and replaces it with more compact code doing exactly the same
thing.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Jagan Teki <jteki@openedev.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Vignesh R <vigneshr@ti.com>

The time command is very helpful for performance and regressions tests.
So lets enable it on SoCrates.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>

This is mandatory, otherwise the USB does not work.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>

The pointer should always be inited to NULL, not zero (0). These are
two different things and not necessarily equal.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Stephen Warren <swarren@nvidia.com>

There could be runtime determined board specific reason why a EHCI
initialization fails (e.g. ENODEV if a Port is not available). In
this case, properly return the error code.
While at it, that function (board_ehci_hcd_init) has actually two
documentation blocks... Use the correct function name for the
documentation block of board_usb_phy_mode.
Signed-off-by: NStefan Agner <stefan@agner.ch>

According PL310 TRM, Auxiliary Control Register
"
The register must be written to using a secure access, and it can be
read using either a secure or a NS access. If you write to this register
with a NS access, it results in a write response with a DECERR response,
and the register is not updated. Writing to this register with the L2
cache enabled, that is, bit[0] of L2 Control Register set to 1,
results in a SLVERR.
"

So If L2 cache is already enabled by ROM, chaning value of ACR
will cause SLVERR and uboot hang.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>