- 12 12月, 2014 10 次提交
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由 Alison Wang 提交于
This patch adds SD boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from SD card to DDR, finally SPL transfer control to u-boot. Signed-off-by: NAlison Wang <alison.wang@freescale.com> Signed-off-by: NJason Jin <jason.jin@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alison Wang 提交于
Through adding CONFIG_QIXIS_I2C_ACCESS macro, QIXIS_READ(reg)/QIXIS_WRITE(reg, value) can be used for both i2c and ifc access to QIXIS FPGA. This is more convenient for coding. Signed-off-by: NJason Jin <jason.jin@freescale.com> Signed-off-by: NAlison Wang <alison.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alison Wang 提交于
Add SUPPORT_SPL feature for SD and NAND boot on LS1021AQDS and LS1021ATWR. Signed-off-by: NAlison Wang <alison.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alison Wang 提交于
On LS1, DDR is initialized by reading SPD through I2C interface in SPL code. For I2C, ll_entry_count() is called, and it returns the number of elements of a linker-generated array placed into subsection of .u_boot_list section specified by _list argument. So add I2C linker list in the generic .lds to fix the issue about using I2C in SPL. Signed-off-by: NAlison Wang <alison.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alison Wang 提交于
In SD boot, the magic number of u-boot image will be checked. For LS102xA, u-boot.bin doesn't have the magic number. So use u-boot.img which includes the magic number instead of u-boot.bin when producing u-boot-with-spl-pbl.bin. Signed-off-by: NAlison Wang <alison.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alison Wang 提交于
For LS102xA, the size of spl/u-boot-spl.bin is variable. This patch adds the support to deal with the variable u-boot size in pblimage tool. It will be padded to 64 byte boundary. Use pblimage_check_params() to add the specific operations for ARM, such as PBI CRC and END command and the calculation of pbl_cmd_initaddr. Signed-off-by: NAlison Wang <alison.wang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Chenhui Zhao 提交于
When resuming from deep sleep, the I2C channel may not be in the default channel. So, switch to the default channel before accessing DDR SPD. Signed-off-by: NChenhui Zhao <chenhui.zhao@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Minghuan Lian 提交于
The patch changes PCIe dts node status to 'disabled' if the corresponding controller is disabled according to serdes protocol. Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 chenhui zhao 提交于
After wakeup from deep sleep, Clear EPU registers as early as possible to prevent from possible issue. It's also safe to clear at normal boot. Signed-off-by: NChenhui Zhao <chenhui.zhao@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Tang Yuantian 提交于
The bus frequency in SOC node should be clock frequency of platform. That is not true if it is devided by 2. Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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- 09 12月, 2014 5 次提交
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由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@ti.com>
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- 08 12月, 2014 25 次提交
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由 Masahiro Yamada 提交于
Some UniPhier boards are equipped with an expansion slot that some optional SRAM/NOR-flash cards can be attached to. So, run-time detection of the number of flash banks would be more user-friendly. Until this commit, UniPhier boards have achieved this by (ab)using board_flash_wp_on() because the boot failed if flash_size got zero. Fortunately, this problem was solved by commit 70879a92 (flash: do not fail even if flash_size is zero). Now it is possible to throw away such a tricky workaround. This commit also enables CONFIG_SYS_MAX_FLASH_BANKS_DETECT for further refactoring. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Masahiro Yamada 提交于
0x20000000-0x2fffffff: assigned to ARM mpcore (sLD3 only) 0xf0000000-0xffffffff: assigned to Denali NAND controller (sLD3 only) Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Masahiro Yamada 提交于
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Masahiro Yamada 提交于
Add I2C controller and NAND controller devices. Fix indentation too. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@ti.com>
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由 Peter Kümmel 提交于
Warning: In file included from scripts/kconfig/zconf.tab.c:2537:0: scripts/kconfig/menu.c: In function ‘get_symbol_str’: scripts/kconfig/menu.c:590:18: warning: ‘jump’ may be used uninitialized in this function [-Wmaybe-uninitialized] jump->offset = strlen(r->s); Simplifies the test logic because (head && local) means (jump != 0) and makes GCC happy when checking if the jump pointer was initialized. Signed-off-by: NPeter Kümmel <syntheticpp@gmx.net> Signed-off-by: NMichal Marek <mmarek@suse.cz> [ imported from Linux Kernel, commit 2d5603060967 ] Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Masahiro Yamada 提交于
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Masahiro Yamada 提交于
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Masahiro Yamada 提交于
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Suriyan Ramasami 提交于
The boot commands - bootz/bootm mandate a third argument which is the address to the FDT blob. In cases where this argument is not specified, boot fails with a message indicating a missing FDT. This causes non-FDT kernels to fail to boot. This patch allows both FDT and non-FDT kernels to boot by making the third parameter to the bootm/bootz optional. Signed-off-by: NSuriyan Ramasami <suriyan.r@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org> [trini: Update again for covering appended DTB case after last revert in this area] Signed-off-by: NTom Rini <trini@ti.com>
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由 Masahiro Yamada 提交于
The macro __iomem is defined in include/linux/compiler.h. Let's include it rather than double __iomem defines. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Cc: Sonic Zhang <sonic.adi@gmail.com>
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由 Masahiro Yamada 提交于
__user and __iomem are defined in include/linux/compiler.h. MAX_ERRNO is defined in include/linux/err.h. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Masahiro Yamada 提交于
Including <linux/compiler.h> is enough for general use. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Daniel Schwierzeck 提交于
Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
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由 angelo@sysam.it 提交于
Signed-off-by: NAngelo Dureghello <angelo@sysam.it>
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由 angelo@sysam.it 提交于
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由 Daniel Schwierzeck 提交于
Introduce a Makefile under arch/$ARCH/ and include it in the top Makefile (similar to Linux kernel). This allows further refactoringi like moving architecture-specific code out of global makefiles, deprecating config variables (CPU, CPUDIR, SOC) or deprecating arch/$ARCH/config.mk. In contrary to Linux kernel, U-Boot defines the ARCH variable by Kconfig, thus the arch Makefile can only included conditionally after the top config.mk. Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Vikas Manocha 提交于
Signed-off-by: NVikas Manocha <vikas.manocha@st.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Vikas Manocha 提交于
pl010 & pl011 have different control register offsets, setting it as per the pl01x type. Signed-off-by: NVikas Manocha <vikas.manocha@st.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Vikas Manocha 提交于
Receive line control uses same setting as transmit line control, also one lcrh write is effective for both baud rate & receive line control internal update. Signed-off-by: NVikas Manocha <vikas.manocha@st.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Vikas Manocha 提交于
UART_IBRD, UART_FBRD, and UART_LCR_H form a single 30-bit wide register which is updated on a single write strobe generated by a UART_LCR_H write. So, to internally update the content of UART_IBRD or UART_FBRD, a write to UART_LCR_H must always be performed at the end. Signed-off-by: NVikas Manocha <vikas.manocha@st.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Vikas Manocha 提交于
Although we were checking the pl01x type, seems like PL010 type was being passed by mistake. Signed-off-by: NVikas Manocha <vikas.manocha@st.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Masahiro Yamada 提交于
The CPU directory of IMX6 is arch/arm/cpu/armv7, so setting CONFIG_SPL_START_S_PATH to arch/arm/cpu/armv7 is totally redundant. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Cc: Stefano Babic <sbabic@denx.de>
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由 Masahiro Yamada 提交于
The CPU directory of this board is arch/powerpc/cpu/mpc5xxx. Without the CONFIG_SPL_START_S_PATH and CONFIG_SPL_LDSCRIPT defines, the same start.o and u-boot-spl.lds are selected by default. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Cc: Stefan Roese <sr@denx.de> Acked-by: NStefan Roese <sr@denx.de>
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