- 30 11月, 2012 1 次提交
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由 Yoshihiro Shimoda 提交于
The function should set BL bit, but it should not clear other flags. So, the patch uses set_bl_bit() instead of a local asm code. Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>
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- 29 11月, 2012 16 次提交
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由 Simon Glass 提交于
We need an extra condition here in case we want to use fdt without the silent console/cmdline editing/post options. It is easier to just remove the #ifdef. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Coreboot boards have an LPC TPM connected, so enable this. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Now that coreboot doesn't need the start16 code, remove it. We need to remove the CONFIG_SYS_X86_RESET_VECTOR option from coreboot.h also. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Gabe Black 提交于
A hook is installed to configure PCI bus bridges as they encountered by u-boot. The hook extracts the secondary bus number from the bridge's config space and then recursively scans that bus. On Coreboot, the PCI bus address space has identity mapping with the physical address space, so declare it as such to ensure that the "pci_map_bar" function used by some PCI drivers is behaving properly. This fixes the EHCI PCI driver initialization on Stumpy. This was tested as follows: Ran the PCI command on Alex, saw devices on bus 0, the OXPCIe 952 on bus 1, and empty busses 2 through 5. This matches the bridges reported on bus 0 and the PCI configuration output from coreboot. Signed-off-by: NGabe Black <gabeblack@chromium.org> Signed-off-by: NVincent Palatin <vpalatin@chromium.org> Signed-off-by: NStefan Reinauer <reinauer@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Vadim Bendebury 提交于
This prevents the preprocessor from complaining when processing variadic macros Signed-off-by: NVadim Bendebury <vbendeb@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NGraeme Russ <graeme.russ@gmail.com>
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由 Gabe Black 提交于
U-boot needs a host controller or "hose" to interact with the PCI busses behind them. This change installs a host controller during initialization of the coreboot "board" which implements some of X86's basic PCI semantics. This relies on some existing generic code, but also duplicates a little bit of code from the sc520 implementation. Ideally we'd eliminate that duplication at some point. It looks like in order to scan buses beyond bus 0, we'll need to tell u-boot's generic PCI configuration code what to do if it encounters a bridge, specifically to scan the bus on the other side of it. Signed-off-by: NGabe Black <gabeblack@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NGraeme Russ <graeme.russ@gmail.com>
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由 Stefan Reinauer 提交于
coreboot.c and coreboot_pci.c don't contain board specific but only coreboot specific code. Hence move it to the coreboot directory in arch/x86/cpu (which should probably be moved out of cpu/ in another commit) Signed-off-by: NStefan Reinauer <reinauer@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Gabe Black 提交于
I suspect these includes were usually available because something else included them earlier or because they were brought in transitively. Change-Id: I6aae2ac94dc792eac6febb4345e8125f69f70988 Signed-off-by: NGabe Black <gabeblack@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Gabe Black 提交于
When running from coreboot we don't want this code. This version works by ifdef-ing out all of the code that would go into those sections and all the code that refers to it. The sections are then empty, and the linker will either leave them empty for the loader to ignore or remove them entirely. Signed-off-by: NGabe Black <gabeblack@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
These are available on other architectures, so add them on x86. Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Graeme Russ 提交于
ilog2 is required by AHCI driver Signed-off-by: NGraeme Russ <graeme.russ@gmail.com> Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Graeme Russ 提交于
Signed-off-by: NGraeme Russ <graeme.russ@gmail.com> Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Graeme Russ 提交于
Putting global data on the stack simplifies the init process (and makes it slightly quicker). During the 'flash' stage of the init sequence, global data is in the CAR stack. After SDRAM is initialised, global data is copied from CAR to the SDRAM stack Signed-off-by: NGraeme Russ <graeme.russ@gmail.com> Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Graeme Russ 提交于
So it can be used as a type in struct global_data and remove an ugly typecast Signed-off-by: NGraeme Russ <graeme.russ@gmail.com> Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NMarek Vasut <marex@denx.de>
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- 28 11月, 2012 23 次提交
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由 York Sun 提交于
Fix a bug introduced by this patch powerpc/mpc85xx: Temporary fix for spin table backward compatibility Should have checked both CONFIG_PPC_SPINTABLE_COMPATIBLE and CONFIG_MP in cpu_init.c. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Timur Tabi 提交于
The documented work-around for P4080 erratum SERDES-9 has been updated. It is now compatible with the work-around for erratum A-4580. This requires adding a few bitfield macros for the BnTTLCRy0 register. Signed-off-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Yuanquan Chen 提交于
Due to SerDes configuration error, if we set the PCI-e controller link width as x8 in RCW and add a narrower width(such as x4, x2 or x1) PCI-e device to PCI-e slot, it fails to train down to the PCI-e device's link width. According to p4080ds errata PCIe-A003, we reset the PCI-e controller link width to x4 in u-boot. Then it can train down to x2 or x1 width to make the PCI-e link between RC and EP. Signed-off-by: NYuanquan Chen <B41889@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Zang Roy-R61911 提交于
board configuration file is included before asm/config_mpc85xx.h. however, CONFIG_FSL_SATA_V2 is defined in asm/config_mpc85xx.h. it will never take effective in the board configuration file for this kind of code : #ifdef CONFIG_FSL_SATA_V2 ... #endif To solve this problem, move CONFIG_FSL_SATA_V2 to board configuration header file. This patch reverts Timur's commit:3e0529f7Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Timur Tabi 提交于
The work-around for erratum A-004580 ("Internal tracking loop can falsely lock causing unrecoverable bit errors") is implemented via the PBI (pre-boot initialization code, typically attached to the RCW binary). This is because the work-around is easier to implement in PBI than in U-Boot itself. It is still useful, however, for the 'errata' command to tell us whether the work-around has been applied. For A-004580, we can do this by verifying that the values in the specific registers that the work-around says to update. This change requires access to the SerDes lane sub-structure in serdes_corenet_t, so we make it a named struct. Signed-off-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Kim Phillips 提交于
by moving compat_strlist into the .bss section. 0xfe004d80 fdt_fixup_crypto_node [u-boot]: 264 Signed-off-by: NKim Phillips <kim.phillips@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 York Sun 提交于
Once u-boot sets the spin table to cache-enabled memory, old kernel which uses cache-inhibit mapping without coherence will not work properly. We use this temporary fix until kernel has updated its spin table code. For now this fix is activated by default. To disable this fix for new kernel, set environmental variable "spin_table_compat=no". After kernel has updated spin table code, this default shall be changed. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 York Sun 提交于
P2041RDB uses common corenet TLB and LAW. However it doesn't have promjet connector. It is necessary to use the same base address for correct LAW address. An offset is added for NOR flash. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 York Sun 提交于
Single rank UDIMM timing has been verified with HMT325U7BFR8C-H9 for speed 800, 900, 1000, 1200, 1300MT/s. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Timur Tabi 提交于
The work-around for erratum A-004849 ("CoreNet fabric (CCF) can exhibit a deadlock under certain traffic patterns causing the system to hang") is implemented via the PBI (pre-boot initialization code, typically attached to the RCW binary). This is because the work-around is easier to implement in PBI than in U-Boot itself. It is still useful, however, for the 'errata' command to tell us whether the work-around has been applied. For A-004849, we can do this by verifying that the values in the specific registers that the work-around says to update. Signed-off-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Timur Tabi 提交于
The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of P3041DS/P5020DS ("Hydra") reference board. Signed-off-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Timur Tabi 提交于
The P5040 has an e5500 core, so CONFIG_SYS_PPC64 should be defined in config_mpc85xx.h. This macro was absent in the initial P5040 patch because it crossed paths with the patch that introduced the macro. Also delete CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC, since it's not used in the upstream U-Boot. It's a holdover from the SDK. Signed-off-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 York Sun 提交于
Move FMAN microcude from 0xEF000000 to 0xEFF40000 to free up the beginning of this virtual bank so that this bank can store RCW or be used together with other banks to store large images. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Andy Fleming 提交于
At some point, a confusion arose about the use of the bit definitions in host_caps for bus widths, and the value in ext_csd. By coincidence, a simple shift could convert between one and the other: MMC_MODE_1BIT = 0, EXT_CSD_BUS_WIDTH_1 = 0 MMC_MODE_4BIT = 0x100, EXT_CSD_BUS_WIDTH_4 = 1 MMC_MODE_8BIT = 0x200, EXT_CSD_BUS_WIDTH_8 = 2 However, as host_caps is a bitmask of supported things, there is not, in fact, a one-to-one correspondence. host_caps is capable of containing MODE_4BIT | MODE_8BIT, so nonsensical things were happening where we would try to set the bus width to 12. The new code clarifies the very different namespaces: host_caps/card_caps = bitmask (MMC_MODE_*) ext CSD fields are just an index (EXT_CSD_BUS_WIDTH_*) mmc->bus_width integer number of bits (1, 4, 8) We create arrays to map between the namespaces, like in Linux. Signed-off-by: NAndy Fleming <afleming@freescale.com> Tested-by: NJaehoon Chung <jh80.chung@samsung.com> Tested-by: NStephen Warren <swarren@nvidia.com>
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由 Andy Fleming 提交于
There were a number of shared files that were using CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and several variants (DDR2, DDR3). A recent patchset added 85xx-specific ones to code which was used by 86xx systems. After reviewing places where these constants were used, and noting that the type definitions of the pointers assigned to point to those addresses were the same, the cleanest approach to fixing this problem was to unify the namespace for the 85xx, 83xx, and 86xx DDR address definitions. This patch does: s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g All 85xx, 86xx, and 83xx have been built with this change. Signed-off-by: NAndy Fleming <afleming@freescale.com> Tested-by: NAndy Fleming <afleming@freescale.com> Acked-by: NKim Phillips <kim.phillips@freescale.com>
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由 Taylor Hutt 提交于
If a malformed 'read' or 'write' command is issued, the Sandbox U-Boot can crash because the command-handling code does no error checking on the number of provided arguments. This change makes the mmc 'erase', 'read' and 'write' commands only function if the proper number of arguments are supplied. Also puts the else assignment at the beginning fo the if() statement to shortens the generated code. This removes an unnecessary jump from the generated code. Signed-off-by: NTaylor Hutt <thutt@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Stephen Warren 提交于
Tegra's MMC driver does DMA, and hence needs cache-aligned buffers. In some cases (e.g. user load commands) this cannot be guaranteed by callers of the MMC APIs. To solve this, modify the Tegra MMC driver to use the new bounce_buffer_*() APIs. Note: Ideally, all U-Boot code will always provide address- and size- aligned buffers, so a bounce buffer will only ever be needed for user- supplied buffers (e.g. load commands). Ensuring this removes the need for performance-sucking bounce buffer cache management and memcpy()s. The one known exception at present is the SCR buffer in sd_change_freq(), which is only 8 bytes long. Solving this requires enhancing struct mmc_data to know the difference between buffer size and transferred data size, or forcing all callers of mmc_send_cmd() to have allocated buffers using ALLOC_CACHE_ALIGN_BUFFER(), which while true in this case, is not enforced in any way at present, and so cannot be assumed by the core MMC code. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Stephen Warren 提交于
The current bouncebuf API requires all parameters to be passed to both bounce_buffer_start() and bounce_buffer_stop(). Modify the bouncebuf start function to accept a state structure as a parameter, and only require that state struct to be passed to the stop function. This simplifies usage of the bounce buffer by clients. Don't modify the data pointer, but rather store the temporary buffer in this state struct. The bouncebuf code ensures that client code can always use a single buffer pointer in the state structure, irrespective of whether a bounce buffer actually had to be allocated. Move cache management logic into the bounce buffer code, so that each client doesn't have to duplicate this. I believe there's no need to invalidate the buffer before a DMA operation, since flushing the cache should prevent any write-backs. Update the MXS MMC driver for this change. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Stephen Warren 提交于
If any driver ever needs to use the bounce buffer API, it always needs to use it. As such, providing a dummy implementation of those APIs when CONFIG_BOUNCE_BUFFER isn't defined does not make sense. Remove the dummy implementation. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Stephen Warren 提交于
Commits 6dc71c8d "MMC: MXS: Toggle the generic bounce buffer on the boards" and 49a627f8 "MMC: Remove the MMC bounce buffer" replaced CONFIG_MMC_BOUNCE_BUFFER with CONFIG_BOUNCE_BUFFER, but missed converting a few boards over to the new option. Fix this. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Mela Custodio 提交于
Bring in the code from Linux kernel. Added to Linux kernel by: commit e08c1694d9e2138204f2b79b73f0f159074ce2f5 Author: Andres Salomon <dilinger@queued.net> Date: Fri Jul 4 10:00:03 2008 -0700 Some HW balks when writing both voltage setting and power up at the same time to SDHCI_POWER_CONTROL register. Signed-off-by: NRommel G Custodio <sessyargc@gmail.com> CC: Andy Fleming <afleming@freescale.com> v2: fix attribution and SOB Signed-off-by: NAndy Fleming <afleming@freescale.com>
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