There are times where we may need more than a few kilobytes of stack
space.  We also will not be using CONFIG_SPL_STACK location prior to DDR
being initialized (CONFIG_SYS_INIT_SP_ADDR is still used there) so pick
a good location within DDR for this to be.  Tested on
OMAP4/AM335x/OMAP5/DRA7xx.
Signed-off-by: NTom Rini <trini@ti.com>

On am335x_evm we only support USBETH for a networking SPL option so move
the rest of the defines under that area as that's the only time we need
(and want) environment support here.
Signed-off-by: NTom Rini <trini@ti.com>

Signed-off-by: NTom Rini <trini@ti.com>

Messages to afleming@freescale.com now bounce, and should be
directed to my personal address at afleming@gmail.com
Signed-off-by: NAndy Fleming <afleming@gmail.com>

The _config part is gone for sure, the _defconfig target could at least
work. I have not verified this for all targets though.

It's easier to Cc Masahiro on Kconfig-related changes with a git-mailrc
alias.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

Reflect the latest build system to doc/README.SPL.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

This document is too old and useless.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

if status register do never set MXC_CSPICTRL_TC, spi_xchg_single
endless loops. Add a timeout here to prevent endless hang.
Signed-off-by: NHeiko Schocher <hs@denx.de>
Cc: Dirk Behme <dirk.behme@gmail.com>
Reviewed-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>

This parameter should also be supported.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Tested-by: NAjay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>

The SPI transaction delay is supposed to be measured from the end of one
transaction to the start of the next. The code does not work that way, so
fix it.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Tested-by: NAjay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>

An incorrect message version is passed to the EC in some cases and the
parameters of one function are switched.

Fix these problems.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Tested-by: NAjay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>

It's usually a common pattern to free() the memory that we allocated.
Implement this here to stop leaking memory.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com>

Add support for re-relocation malloc() in arm's start-up code.
Signed-off-by: NSimon Glass <sjg@chromium.org>

At present arm defines CONFIG_SYS_GENERIC_GLOBAL_DATA, meaning that
the global_data pointer is set up in board_init_f(). However it is
actually set up before this, it just isn't zeroed.

If we zero the global data before calling board_init_f() then we
don't need to define CONFIG_SYS_GENERIC_GLOBAL_DATA.

Make this change (on arm32 only) to simplify the init process. I
don't have the ability to test aarch64 yet.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Acked-by: NTom Rini <trini@ti.com>

This patch configures the qrio to trigger a core reset on
a CPU reset request.
Signed-off-by: NRainer Boschung <rainer.boschung@keymile.com>
Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

To acheive this, the qrio_uprstreq() function that sets the UPRSTREQN
flag in the qrio RESCNF reg is added.
Signed-off-by: NRainer Boschung <rainer.boschung@keymile.com>
Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Check the core timer status register (TSR) for watchdog reset,
and and set the QRIO's reset reason flag REASON1[0] accordingly.

This allows the appliction SW to identify the cpu watchdog as a
reset reason, by setting the REASON1[0] flag in the QRIO.
Signed-off-by: NRainer Boschung <rainer.boschung@keymile.com>
Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

To achieve this, the qrio_cpuwd_flag() function that sets the CPU watchdog
flag in the REASON1 reg is added.
Signed-off-by: NRainer Boschung <rainer.boschung@keymile.com>
Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

The booting of the board is now protected by the CPU watchdog.
A failure during the boot phase will end up in board reset.
Signed-off-by: NRainer Boschung <rainer.boschung@keymile.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

When CONFIG_WATCHDOG is defined the board initialization just performs
a WATCHDOG_RESET, an initialization of the watchdog is not done.
This has been modified fot the MPC85xx, the board initialization calls
its watchdog initialitzation allowing for full watchdog configuration
very early in the boot phase.
Signed-off-by: NRainer Boschung <rainer.boschung@keymile.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Function to inititialize the cpu watchdog added.
Signed-off-by: NRainer Boschung <rainer.boschung@keymile.com>
[York Sun: Add prototype in watchdog.h]
Reviewed-by: NYork Sun <yorksun@freescale.com>

For e500mc cores the watchdog timer period has to be set by means of a
6bit value, that defines the bit of the timebase counter used to signal
a watchdog timer exception on its 0 to 1 transition.
The macro used to set the watchdog period TCR_WP, was redefined for e500mc
to support 6 WP setting.

The parameter (x) given to the macro specifies the prescaling factor of
the time base clock (fTB):

watchdog_period = 1/fTB * 2^x
Signed-off-by: NRainer Boschung <rainer.boschung@keymile.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

TCR watchdog bit are overwritten when dec interrupt is enabled.
This has been fixed with this patch.
Signed-off-by: NRainer Boschung <rainer.boschung@keymile.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Add callback with __weak annotation to allow setup of environment
partition number in runtime from a board file.

Propagate mmc_switch_part() return value into init_mmc_for_env() instead
of -1 in case of failure.
Signed-off-by: NDmitry Lifshitz <lifshitz@compulab.co.il>
Signed-off-by: NIgor Grinberg <grinberg@compulab.co.il>
Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>

Add missing mmc_get_env_addr() prototype in environment.h
Signed-off-by: NDmitry Lifshitz <lifshitz@compulab.co.il>
Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>

If the MCI IP version >= 0x300, it supports hight speed mode
option, this patch enable it.
Signed-off-by: NBo Shen <voice.shen@atmel.com>
Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>

Add configuration register definition, this register only
exists on MCI IP version >= 0x300.
Signed-off-by: NBo Shen <voice.shen@atmel.com>
Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>

The mode register is different between MCI IP version.
So, according to MCI IP version to set the mode register.
Signed-off-by: NBo Shen <voice.shen@atmel.com>
Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>

To fix the clock divider calculation error when the controller
clock same as the operating frequency. This is known as bypass
mode. In this mode, the divider should be 0.
Signed-off-by: NChin Liang See <clsee@altera.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Mischa Jonker <mjonker@synopsys.com>

Implement SD driver for the S3C24xx family. This implementation
is currently only capable of using the PIO transfers, DMA is not
supported.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>

Unify the register structure so they can be easily used across all
of S3C24xx lineup.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>

Seems like the controller doesn't support the flag. None of the hi-speed cards
I've tried could be read, while they successfully worked with the quirk enabled.
Signed-off-by: NLubomir Rintel <lkundrak@v3.sk>
Tested-by: NStephen Warren <swarren@wwwdotorg.org>

This patch add Marvell kirkwood MVSDIO/MMC driver
and enable it for Sheevaplugs and OpenRD boards.
Signed-off-by: NGerald Kerma <drEagle@doukki.net>
Reviewed-by: NStefan Roese <sr@denx.de>
Acked-by: NPantelis Antoniou <panto@antoniou-consulting.com>

The Banana Pi is an A20 based development board using Raspberry Pi compatible
IO headers. It comes with 1 GB RAM, 1 Gb ethernet, 2x USB host, sata, hdmi
and stereo audio out + various expansion headers:

http://www.lemaker.org/Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

CNTFRQ needs to be properly configured on all CPUs. Otherwise,
virtual machines hoping to find valuable information on secondary
CPUs will be disapointed...
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Acked-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>