- 15 6月, 2007 1 次提交
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由 Stefan Roese 提交于
The board config array CFG_440_GPIO_TABLE for the ppc440 GPIO setup is extended with the default GPIO output state (level). Signed-off-by: NStefan Roese <sr@denx.de>
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- 14 6月, 2007 1 次提交
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由 Stefan Roese 提交于
Now program_tlb() allows to program a TLB (or multiple) with different virtual and physical addresses. With this change, now one physical region (e.g. SDRAM) can be mapped 2 times, once with caches diabled and once with caches enabled. Signed-off-by: NStefan Roese <sr@denx.de>
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- 08 6月, 2007 1 次提交
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由 Benoît Monin 提交于
Set the correct value in GPIOx_TCR when configuring the gpio with CFG_440_GPIO_TABLE. Signed-off-by: NBenoit Monin <bmonin@adeneo.eu> Signed-off-by: NStefan Roese <sr@denx.de>
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- 06 6月, 2007 7 次提交
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由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de>
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由 Wolfgang Denk 提交于
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由 Wolfgang Denk 提交于
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由 Stefan Roese 提交于
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由 Stefan Roese 提交于
This patch adds NAND booting support for the AMCC Acadia eval board. Please make sure to configure jumper J7 to position 2-3 when booting from NOR, and to position 1-2 when booting for NAND. I also added a board command to configure the I2C bootstrap EEPROM values. Right now only 267MHz is support for booting either via NOR or NAND FLASH. Here the usage: => bootstrap 267 nor ;to configure the board for 267MHz NOR booting => bootstrap 267 nand ;to configure the board for 267MHz NNAND booting Signed-off-by: NStefan Roese <sr@denx.de>
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由 Jon Loeliger 提交于
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由 Ed Swarthout 提交于
e600 does not have a bootpg restriction. Move the version string to beginning of image at fff00000. Resetvec.S is not needed. Update flash copy instructions. Add tftpflash env variable Signed-off-by: NEd Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: NJon Loeliger <jdl@freescale.com>
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- 05 6月, 2007 1 次提交
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由 Wolfgang Denk 提交于
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- 04 6月, 2007 1 次提交
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由 Benoît Monin 提交于
The attached patch is mainly cosmetic, allowing u-boot to display the correct bootstrap option letter according to the datasheets. The original patch was extended with 405EZ support by Stefan Roese. Signed-off-by: NBenoit Monin <bmonin@adeneo.eu> Signed-off-by: NStefan Roese <sr@denx.de>
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- 01 6月, 2007 13 次提交
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
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由 Stefan Roese 提交于
This patch undoes the patch by Jeff Mann with commit-id ada4697d. As suggested by AMCC it is not recommended to dynamically change the EBC speed after bootup. So we undo this change to be on the safe side. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
This patch adds NAND booting support for the AMCC Bamboo eval board. Since the NAND-SPL boot image is limited to 4kbytes, this version only supports the onboard 64MBytes of DDR. The DIMM modules can't be supported, since the setup code for I2C DIMM autodetection and configuration is too big for this NAND bootloader. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
The U-Boot NAND booting support is now extended to support ECC upon loading of the NAND U-Boot image. Tested on AMCC Sequoia (440EPx) and Bamboo (440EP). Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
This patch updates the "normal" Bamboo NOR booting port, so that it is compatible with the coming soon NAND booting Bamboo port. It also enables the 2nd NAND flash on the Bamboo. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
This patch adds hardware ECC support to the NDFC driver. It also changes the register access from using the "simple" in32/out32 functions to the in_be32/out_be32 functions, which make sure that the access is correctly synced. This is the only recommended access to SoC registers in the current Linux kernel. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
This patch updates the nand_ecc code to the latest Linux version. The main reason for this is the more compact code. This makes it possible to include the ECC code into the NAND bootloader image (NAND_SPL) for PPC4xx. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
With the updated 44x DDR2 driver the Luan board now supports ECC generation and checking. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Add config option for 180 degree advance clock control as needed for the AMCC Luan eval board. Signed-off-by: NStefan Roese <sr@denx.de>
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- 31 5月, 2007 2 次提交
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由 Wolfgang Denk 提交于
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由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de>
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- 28 5月, 2007 1 次提交
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由 Wolfgang Denk 提交于
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- 27 5月, 2007 10 次提交
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由 Bartlomiej Sieka 提交于
Signed-off-by: NBartlomiej Sieka <tur@semihalf.com>
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由 Bartlomiej Sieka 提交于
Enable redundant environment, add a MTD partition for it; also add env. variable command for passing MTD partitions to the kernel command line. Signed-off-by: NPiotr Kruszynski <ppk@semihalf.com> Acked-by: NBartlomiej Sieka <tur@semihalf.com>
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由 Bartlomiej Sieka 提交于
Allow passing longer command line to the kernel - useful especially for passing MTD partition layout. Signed-off-by: NPiotr Kruszynski <ppk@semihalf.com> Acked-by: NBartlomiej Sieka <tur@semihalf.com>
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由 Bartlomiej Sieka 提交于
Signed-off-by: NPiotr Kruszynski <ppk@semihalf.com> Acked-by: NBartlomiej Sieka <tur@semihalf.com>
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由 Bartlomiej Sieka 提交于
Change EEPROM configuration according to the datasheet: "The 24C01A and 24C02A have a page write capability of two bytes", and "This device offers fast (1ms) byte write". Add 3ms of extra delay. Signed-off-by: NPiotr Kruszynski <ppk@semihalf.com> Acked-by: NBartlomiej Sieka <tur@semihalf.com>
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由 Bartlomiej Sieka 提交于
After being reset in mpc5xxx_fec_init_phy(), PHY goes into FX mode, in which networking does not function. This commit switches PHY to TX mode by clearing the FX_SEL bit of Mode Control Register. It also reverses commit 008861a2, i.e., a temporary workaround. Signed-off-by: NGrzegorz Bernacki <gjb@semihalf.com> Acked-by: NBartlomiej Sieka <tur@semihalf.com>
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由 Bartlomiej Sieka 提交于
Signed-off-by: NPiotr Kruszynski <ppk@semihalf.com> Acked-by: NBartlomiej Sieka <tur@semihalf.com>
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由 Bartlomiej Sieka 提交于
Signed-off-by: NJan Wrobel <wrr@semihalf.com> Acked-by: NBartlomiej Sieka <tur@semihalf.com>
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由 Bartlomiej Sieka 提交于
Both CFG_PCISPEED_66 and CFG_IPBSPEED_133 are misnamed, as defining them does not cause PCI or IPB clocks to run at the specified speed. Instead, they configure divisors used to calculate said clocks. This patch renames the defines according to their real function. Signed-off-by: NGrzegorz Bernacki <gjb@semihalf.com> Acked-by: NBartlomiej Sieka <tur@semihalf.com>
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由 Bartlomiej Sieka 提交于
Signed-off-by: NJan Wrobel <wrr@semihalf.com> Signed-off-by: NMarian Balakowicz <m8@semihalf.com> Acked-by: NBartlomiej Sieka <tur@semihalf.com>
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- 24 5月, 2007 2 次提交
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由 Stefan Roese 提交于
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由 Stefan Roese 提交于
As pointed out by Bruce Adler <bruce.adler@acm.org> this patch fixes a small bug in the 405EZ OCM initialization. Thanks for spotting. Signed-off-by: NStefan Roese <sr@denx.de>
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