- 12 3月, 2007 1 次提交
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由 Aubrey Li 提交于
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- 10 3月, 2007 1 次提交
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由 Aubrey Li 提交于
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- 09 3月, 2007 6 次提交
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由 Aubrey.Li 提交于
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由 Aubrey.Li 提交于
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由 Wolfgang Denk 提交于
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由 Wolfgang Denk 提交于
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由 Wolfgang Denk 提交于
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由 Wolfgang Denk 提交于
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- 08 3月, 2007 6 次提交
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由 Wolfgang Denk 提交于
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由 Stefan Roese 提交于
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由 Stefan Roese 提交于
The AMCC Luan now uses the common 440SP(e) DDR SPD code for DDR inititializition. This includes DDR auto calibration and support for different DIMM modules, instead of the fixed setup used in the earlier version. This patch also enables the cache in FLASH for the startup phase of U-Boot (while running from FLASH). After relocating to SDRAM the cache is disabled again. This will speed up the boot process, especially the SDRAM setup, since there are some loops for memory testing (auto calibration). Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
The AMCC Yucca now uses the common 440SP(e) DDR SPD code for DDR inititializition. This includes DDR auto calibration and support for different DIMM modules, instead of the fixed setup used in the earlier version. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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- 07 3月, 2007 7 次提交
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由 Wolfgang Denk 提交于
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由 Stefan Roese 提交于
Define CONFIG_PROG_SDRAM_TLB so that the TLB entries for the DDR memory are dynamically programmed matching the total size of the equipped memory (DIMM modules). Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
This patch fixes a problem that occurs when 2 DIMM's are used. This problem was first spotted and fixed by Gerald Jackson <gerald.jackson@reaonixsecurity.com> but this patch fixes the problem in a little more clever way. This patch also adds the nice functionality to dynamically create the TLB entries for the SDRAM (tlb.c). So we should never run into such problems with wrong (too short) TLB initialization again on these platforms. As this feature is new to the "old" 44x SPD DDR driver, it has to be enabled via the CONFIG_PROG_SDRAM_TLB define. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Wolfgang Denk 提交于
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由 Wolfgang Denk 提交于
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由 Wolfgang Denk 提交于
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由 Wolfgang Denk 提交于
Patch by Mike Frysinger, Mar 05 2007
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- 06 3月, 2007 1 次提交
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由 Stefan Roese 提交于
As provided by the AMCC applications team, this patch optimizes the DDR2 setup for 166MHz bus speed. The values provided are also save to use on a "normal" 133MHz PLB bus system. Only the refresh counter setup has to be adjusted as done in this patch. For this the NAND booting version had to include the "speed.c" file from the cpu/ppc4xx directory. With this addition the NAND SPL image will just fit into the 4kbytes of program space. gcc version 4.x as provided with ELDK 4.x is needed to generate this optimized code. Signed-off-by: NStefan Roese <sr@denx.de>
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- 03 3月, 2007 18 次提交
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由 Kim Phillips 提交于
(cherry picked from c5bf13b02284c3204a723566a9bab700e5059659 commit)
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由 Kumar Gala 提交于
The config value for: * CFG_ACR_PIPE_DEP * CFG_ACR_RPTCNT * CFG_SPCR_TSEC1EP * CFG_SPCR_TSEC2EP * CFG_SCCR_TSEC1CM * CFG_SCCR_TSEC2CM Were not being used when setting the appropriate register Added: * CFG_SCCR_USBMPHCM * CFG_SCCR_USBDRCM * CFG_SCCR_PCICM * CFG_SCCR_ENCCM To allow full config of the SCCR. Also removed random CFG_SCCR settings in MPC8349EMDS, TQM834x, and sbc8349 that were just bogus. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Kim Phillips 提交于
8360 and 832x weren't updating their [local-]mac-address properties. This patch fixes that. Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Timur Tabi 提交于
Some device trees have a mac-address property, some have local-mac-address, and some have both. To support all of these device trees, this patch updates ftp_cpu_setup() to write the MAC address to mac-address if it exists. This function already updates local-mac-address. Signed-off-by: NTimur Tabi <timur@freescale.com>
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由 Kim Phillips 提交于
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由 Kim Phillips 提交于
Disable G1TXCLK, G2TXCLK h/w buffers. This patch fixes a networking timeout issue with MPC8360EA (Rev.2) PBs. Verified on Rev. 1.1, Rev. 1.2, and Rev. 2.0 boards. Signed-off-by: NKim Phillips <kim.phillips@freescale.com> Signed-off-by: NEmilian Medve <Emilian.Medve@freescale.com>
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由 Xie Xiaobo 提交于
The code supply fixed and SPD initialization for MPC83xx DDR2 Controller. it pass DDR/DDR2 compliance tests. Signed-off-by: NXie Xiaobo <X.Xie@freescale.com>
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由 Xie Xiaobo 提交于
MPC8360E rev2.0 have new spridr,and PVR value, The MDS board for MPC8360E rev2.0 has 32M bytes Flash and 256M DDR2 DIMM. Signed-off-by: NXie Xiaobo <X.Xie@freescale.com>
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由 Xie Xiaobo 提交于
MPC8349E rev3.1 have new spridr,and PVR value, The MDS board for MPC8349E rev3.1 has 32M bytes Flash and 256M DDR2 DIMM. Signed-off-by: Xie Xiaobo<X.Xie@freescale.com>
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由 Joakim Tjernlund 提交于
Fix empty i2c reads/writes, i2c_write(0x50, 0x00, 0, NULL, 0) which is used to se if an slave will ACK after receiving its address. Correct i2c probing to use this method as the old method could upset a slave as it wrote a data byte to it. Add a small delay in i2c_init() to let the controller shutdown any ongoing I2C activity. Signed-off-by: NJoakim Tjernlund <Joakim.Tjernlund@transmode.se>
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由 Timur Tabi 提交于
Add support for the MPC8349E-mITX-GP, a stripped-down version of the MPC8349E-mITX. Bonus features include support for low-boot (BMS bit in HRCW is 0) for the ITX and a README for the ITX and the ITX-GP. Signed-off-by: NTimur Tabi <timur@freescale.com>
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由 Timur Tabi 提交于
There is no SDRAM on any of the 8349 ITX variants, so function sdram_init() never does anything. This patch deletes it. Signed-off-by: NTimur Tabi <timur@freescale.com>
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由 Dave Liu 提交于
The patch solves the alignment problem of the local bus access windows to render accessible the memory bank and PHY registers of UPC 1 (starting at 0xf801 0000). What we actually did was to adjust the sizes of the bus access windows so that the base address alignment requirement would be met. Signed-off-by: NChereji Marian <marian.chereji@freescale.com> Signed-off-by: NGridish Shlomi <gridish@freescale.com> Signed-off-by: NDave Liu <daveliu@freescale.com>
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由 Kim Phillips 提交于
don't hang if watchdog configured on 8360, 832x The watchdog programming model is the same across all 83xx devices; make the code reflect that.
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由 Kim Phillips 提交于
protect memcpy to bad address if a local-mac-address is missing from dt
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由 Kim Phillips 提交于
make 8360 default environment fdt be 8360 (not 8349)
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由 Emilian Medve 提交于
The problem is not gcc4 but the code itself. The BD_STATUS() macro can't be used for busy-waiting since it strips the 'volatile' property from the bd variable. gcc3 was working by pure luck. This is a follow on patch to "Fix the UEC driver bug of QE"
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由 Kumar Gala 提交于
The code that is ifdef'd with CONFIG_MPC8349 is actually applicable to all MPC834X class processors. Change the protections from CONFIG_MPC8349 to CONFIG_MPC834X so they are more generic. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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