- 18 12月, 2018 5 次提交
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由 Bin Meng 提交于
Add the QEMU RISC-V platform-specific Kconfig options, to include CPU and timer drivers. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: NAnup Patel <anup@brainfault.org>
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由 Anup Patel 提交于
This adds an implementation of riscv_get_time() API that is using rdtime instruction. This is the case for S-mode U-Boot, and is useful for processors that support rdtime in M-mode too. Signed-off-by: NAnup Patel <anup@brainfault.org> Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>
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由 Bin Meng 提交于
This adds U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT). The CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. This driver implements the riscv_get_time() API as required by the generic RISC-V timer driver, as well as some other APIs that are needed for handling IPI. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: NAnup Patel <anup@brainfault.org>
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由 Anup Patel 提交于
So far we have a Kconfig option for supervisor mode. This adds an option for the machine mode. Signed-off-by: NAnup Patel <anup@brainfault.org> Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>
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由 Lukas Auer 提交于
RISC-V has two code models, medium low (medlow) and medium any (medany). Medlow limits addressable memory to a single 2 GiB range between the absolute addresses -2 GiB and +2 GiB. Medany limits addressable memory to any single 2 GiB address range. By default, medlow is selected for U-Boot on both 32-bit and 64-bit systems. The -mcmodel compiler flag is selected according to the Kconfig configuration. Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de> [bmeng: adjust to make medlow the default code model for U-Boot] Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NAnup Patel <anup@brainfault.org>
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- 05 12月, 2018 1 次提交
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由 Anup Patel 提交于
This patch adds kconfig option RISCV_SMODE to run U-Boot in S-mode. When this opition is enabled we use s<xyz> CSRs instead of m<xyz> CSRs. It is important to note that there is no equivalent S-mode CSR for misa and mhartid CSRs so we expect M-mode runtime firmware (BBL or equivalent) to emulate misa and mhartid CSR read. In-future, we will have more patches to avoid accessing misa and mhartid CSRs from S-mode. Signed-off-by: NAnup Patel <anup@brainfault.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Tested-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>
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- 26 11月, 2018 4 次提交
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由 Rick Chen 提交于
AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: NRick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
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由 Lukas Auer 提交于
Add Kconfig entries for the C (compressed instructions) and A (atomic instructions) ISA extensions. Only the C ISA extension is selectable. This matches the configuration in Linux. The Kconfig entries are not used yet. A follow-up patch will select the appropriate compiler flags based on the Kconfig configuration. Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Lukas Auer 提交于
CONFIG_PHYS_64BIT should be enabled on RV64I systems. Select it. Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NRick Chen <rick@andestech.com>
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由 Lukas Auer 提交于
RISC-V defines the base integer instruction sets as RV32I and RV64I. Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to match this convention. Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NRick Chen <rick@andestech.com>
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- 03 10月, 2018 2 次提交
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由 Bin Meng 提交于
This adds QEMU RISC-V 'virt' board target support, with the hope of helping people easily test U-Boot on RISC-V. The QEMU virt machine models a generic RISC-V virtual machine with support for the VirtIO standard networking and block storage devices. It has CLINT, PLIC, 16550A UART devices in addition to VirtIO and it also uses device-tree to pass configuration information to guest software. It implements RISC-V privileged architecture spec v1.10. Both 32-bit and 64-bit builds are supported. Support is pretty much preliminary, only booting to U-Boot shell with the UART driver on a single core. Booting Linux is not supported yet. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>
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由 Bin Meng 提交于
It's RISC-V that is the official name, not RISCV. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: NRick Chen <rick@andestech.com>
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- 29 5月, 2018 1 次提交
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由 Rick Chen 提交于
Andes has rearranged the product combinations. nx25 and ax25 both are RISC-V architecture cpu core. But ax25 has MMU unit inside, and nx25 is not. Cpu nx25 and platform ae250 are arranged in pairs. Cpu ax25 and platform ae350 are arranged in pairs. This patch will rename nx25 as ax25 ae250 as ae350 nx25-ae250 as ax25-ae350 including filename, variable, string and definition. Then u-boot can boot linux kernel in ae350 platform reasonably. Signed-off-by: NRick Chen <rick@andestech.com> Signed-off-by: NRick Chen <rickchen36@gmail.com> Cc: Greentime Hu <green.hu@gmail.com>
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- 12 1月, 2018 1 次提交
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由 Rick Chen 提交于
Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: NRick Chen <rick@andestech.com> Signed-off-by: NRick Chen <rickchen36@gmail.com> Signed-off-by: NGreentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
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