Update the configuration files to support the device tree and driver
model. The device clock and pins configuration are handled by the
clock and the pinctrl drivers respectively.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Since the introduction of the pinctrl and clk drivers and the
device tree files, remove unneeded hard coded related code from
the board file.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Update the configuration files to support the device tree and driver
model. The device clock and pins configuration are handled by the
clock and the pinctrl drivers respectively.

Because the limitation of internal SRAM size, the SPL with driver
model can't be supported, disable the SPL option.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Since the introduction of the pinctrl and clk driver and the device
tree files, remove unneeded related code from the board file.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Update the configuration files to support the device tree and driver
model. The device clock and pins configuration are handled by the
clock and the pinctrl drivers respectively.

Because the limitation of internal SRAM size, the SPL with driver
model can't be supported, disable the SPL option.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Since the introduction of the pinctrl and clock driver and the device
tree files, remove unneeded hard coded related code from the board
file.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Update the configuration files to support the device tree and driver
model. The device clock and pins configuration are handled by the
clock and the pinctrl drivers respectively.

Because the limitation of internal SRAM size, the SPL with driver
model can't be supported, disable the SPL option.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The device tree source files of at91sam9263ek boards are copied from
the Linux v4.10, do the changes as below.
 - Add the reg property for the pinctrl node.
 - Move the gpio (pioA, pioB, pioC, pioD, pioE) nodes as the pinctrl's
   slibling nodes, instead of the child nodes.
 - Add the "u-boot,dm-pre-reloc" property for the dbgu node are used
   in board_init_f stage.
 - Fix the compilation warnings.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The device tree source files of at91sam9rlek boards are copied from
the Linux v4.10, do the changes as below.
 - Add the reg property for the pinctrl node.
 - Move the gpio (pioA, pioB, pioC, pioD) nodes as the pinctrl's
   slibling nodes, instead of the child nodes.
 - Add the "u-boot,dm-pre-reloc" property for the dbgu node are used
   in board_init_f stage.
 - Fix the compilation warnings.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The device tree source files of at91sam9g20ek and at91sam9260ek
boards are copied from the Linux v4.10, do the changes below.
 - Fix the build error for the usb0 node.
 - Add the reg property for the pinctrl node.
 - Move the gpio (pioA, pioB, pioC ...) nodes as the pinctrl's
   slibling nodes, instead of the child nodes.
 - Add the "u-boot,dm-pre-reloc" property for the dbgu node are used
   in board_init_f stage.
 - Add the clk pinctrl of the mmc0 node.
 - Fix the compilation warnings.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The device tree source files of at91sam9m10g45ek boards are copied
from the Linux v4.10, do the changes as below.
 - Add the reg property for the pinctrl node.
 - Move the gpio (pioA, pioB, pioC, pioD, pioE) nodes as the pinctrl's
   slibling nodes, instead of the child nodes.
 - Add the "u-boot,dm-pre-reloc" property to determine which nodes
   are used by the board_init_f stage.
 - Fix the compilation warnings.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The device tree source files of at91sam9n12ek boards are copied from
the Linux v4.10, do the changes as below.
 - Add the reg property for the pinctrl node.
 - Move the gpio (pioA, pioB, pioC, pioD) nodes as the pinctrl's
   slibling nodes, instead of the child nodes.
 - Change the compatible of the spi flash to "spi-flash".
 - Add the spi0 aliases.
 - Fix the pinctrl-names of mmc0 node.
 - Add the "u-boot,dm-pre-reloc" property to determine which nodes
   are used by the board_init_f stage.
 - Fix the compilation warnings.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The device tree source files of at91sam9x5ek board are copied from
the Linux v4.10, do the changes below.
 - Add the reg property for the pinctrl node.
 - Move the gpio (pioA, pioB, pioC ...) nodes as the pinctrl's
   slibling nodes, instead of the child nodes.
 - Add the "u-boot,dm-pre-reloc" property to determine which nodes
   are used by the board_init_f stage.
 - Change the compatible of the spi flash to "spi-flash".
 - Add the spi0 aliases.
 - Fix the compilation warnings.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Add the clock support.
Note that the clock handling of the DBGU peripheral is different
from the USART.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Add the uart init function to be used on both probe and the early
debug uart init. For the latter, the input clock should be from
CONFIG_DEBUG_UART_CLOCK.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Align the at91 pmc's compatibles with kernel.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NAndreas Bießmann <andreas@biessmann.org>

Add the compatible "atmel,at91rm9200-clk-master" to align with
the kernel.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Enhance the peripheral clock to support both at9sam9x5's and
at91rm9200's peripheral clock via the different compatibles.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Add the compatibles to align with the kernel.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

To avoid the failure of mdio_register(), add the remove callback
to unregister the mii_dev when removing the ethernet device.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Fixed up unused variable warning, e.g. for gurnard:
Signed-off-by: NSimon Glass <sjg@chromium.org>

The sama5d36ek CMP board is the variant of sama5d3xek board.
It is equipped with the low-power DDR2 SDRAM, PMIC ACT8865, and
some power rails. The board is mainly used to measure the power
consumption. As all those changes are done in at91bootstrap,
in U-Boot, only use another device tree file, no code needed
to change.

As there is additional power consumption when enbling the USB
Host and USB device, for the power consumption measurement
intention, disable the USB host and device.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>

Fix the DDR2 configuration to make SPL work.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>

Enable config options to support the SPL, increase the malloc
memory size for the SPL and board_init_f stage and increase
the memory space for the SPL binary.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>

Remove the unnecessary header files.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>

Due to the pin configuration and clock enabling is handling by the
driver, remove the unneeded hardcode uart1 init during
board_early_init_f stage.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>

Because the MACB driver supports the driver model and device tree,
the pins configuration and clock enabling are handled by the
pinctrl driver and clock driver, remove this hardcoded init code.

The USB Ether init code is removed as well.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>

Enable CONFIG_DM_ETH to make MACB to support driver model.

Because the USB Ether doesn't support driver model so far,
remove this feature.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>

Add the "u-boot,dm-pre-reloc" property to determine which nodes
which are needed by SPL and by the board_init_f stage.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>

Add clock property for uart1 node.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>

With gcc-6 we see a warning that sysclk_tbl is defined but unused, so
remove it.

Cc: York Sun <york.sun@nxp.com>
Signed-off-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

- Remove "probe" function from sandbox wdt driver
- Fix include order

Fixes: 0753bc2d ("dm: Simple Watchdog uclass")
Signed-off-by: NMaxim Sloyko <maxims@google.com>
[trini: Create as the delta between v1 (applied) and v2 (should have
 applied)].
Signed-off-by: NTom Rini <trini@konsulko.com>

One some keystone2 platforms like K2G ICE, there is an option
to switch between 24MHz or 25MHz as sysclk. But the existing
driver assumes it is always 24MHz. Add support for getting
all reference clocks dynamically by reading boot pins.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

K2G supports various sysclk frequencies which can be
determined using sysboot pins. PLLs should be configured
based on this sysclock frequency. Add PLL configurations
for all supported sysclk frequencies.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Enable TI_COMMON_CMD_OPTIONS on all keystone2 platforms.
Also sync with savedefconfig.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

Enable TI_COMMON_CMD_OPTIONS on all dra7xx platforms.
Also sync with savedefconfig.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>