Move frequency-dependent register settings to arrays for clean-up.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The if-else statements for the frequency-dependent register settings
seem clumsy.  Moving them to arrays would make it cleaner.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The DDR PHY settings no longer depend on the DRAM size.  Drop the
argument from the init function.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Now these three are almost the same.  The only difference is the DTPR1
register dependency on the DRAM size, but it can be ignored.  (It has
already been ignored in PH1-sLD8 and PH1-Pro4.)
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Add a field to distinguish DDR3+ from (standard) DDR3.  It also
allows to delete CONFIG_DDR_STANDARD (this is not a software
configuration, but a board attribute).

Default DDR3 spec for each SoC:

  PH1-LD4, PH1-sLD8: DDR3+
  Others: DDR3
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

These settings control the clocks around the memory controller.
The debug ability is unneeded once it works properly.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

These settings were used only for the PH1-sLD3 and older SoCs.  The
PH1-LD4 and newer one just ignore them because their DDR-PHY take
care of such timing parameters instead.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Currently, a dummy value is defined for the UMC_SPCCTLA register
when the DRAM size is zero.  This seems weird because the controller
does not need setting in the first place if the size is zero.

Also, redefine enum dram_size to represent the DRAM size per 16-bit
unit.  This makes things simpler because the channel 0 and 1 are
connected with 32-bit width DRAM, while the channel 2 is connected
with 16-bit width one.

I am renaming SIZE_* into DRAM_SZ_* (and also FREQ_* to DRAM_FREQ_*
for consistency) while I am here because SIZE_* might be easily
mixed-up with the macros in include/linux/sizes.h.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Now this code can be re-written with a "for" statement instead of
calling the same function multiple times.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This commit reworks "struct uniphier_board_data" with an array of
DRAM channel data in it.  It will allow further cleanups by means of
"for" statements that iterate over the DDR channels.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This function is unused.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Of the several boot devices supported, it looks like the eMMC is the
most commonly used.  Enable CONFIG_ENV_IS_IN_MMC by default.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The Boot ROM expects the boot image (SPL) in the Boot Partition 1.
So, updating images involves the hardware partition switch.  It might
be a bit advanced for some users.

To be user-friendly, this commit adds a useful command to update the
images; just put SPL and U-Boot proper into the public directory of
the TFTP server and execute "run emmcupdate" from the command line.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

UniPhier SoC family supports both (e)MMC boot and SD card boot;
however, both of them are handled in the same uclass.

When booting from the eMMC, we want to know the device number
of the (e)MMC, not SD.  This command is useful to find the first
MMC (non-SD) device.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Export device nodes needed for eMMC boot (eMMC node, pinctrl, and
clock) to the SPL DTB.  CONFIG_SUPPORT_EMMC_BOOT is also necessary
to use "mmc partconf" command.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This host controller is available for all UniPhier SoCs.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Enable the driver in all UniPhier defconfig files and add some
needed defines to the common files.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Add a driver for the on-chip SD/eMMC host controller used by
UniPhier SoC family.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Make the GPIO driver really active.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This allows to use the "gpio" command.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: NSimon Glass <sjg@chromium.org>

I implemented a GPIO driver based on Driver Model for the UniPhier
SoC family, but I could not find any good reason why such SoC
specific GPIO headers are needed.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: NSimon Glass <sjg@chromium.org>

This GPIO controller device is used on UniPhier SoCs.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Follow the changes of DTS in Linux.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

There is currently one config option (CONFIG_NET_RETRY_COUNT) that
is available to tune the retries of the network stack.
Unfortunately, it is global to all protocols, and the value is
interpreted differently in all of them.

Add a new environment variable that directly sets the retry period for
BOOTP timeouts. If this new value is not set, the period is still derived
from the default number of retries, or from CONFIG_NET_RETRY_COUNT if
defined. When both the new variable is set and CONFIG_NET_RETRY_COUNT
is defined, the variable has precedence.
Signed-off-by: NAlexandre Messier <amessier@tycoint.com>

In commit <a058052c> [net: phy: do not read configuration register on
reset], phy_reset() will clear the BMCR register. Bit 12(AUTO_NEGOTIATION)
is cleared too. It causes auto-negotiation timeout error on Atheros's
PHY AR8033.

To fix this problem, genphy_config_aneg() and genphy_restart_aneg()
needs to be called in ar8035_config() to enable and restart
auto-negotiation.
Signed-off-by: NAlison Wang <alison.wang@nxp.com>
Acked-by: NStefan Agner <stefan@agner.ch>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

The patch that enabled eSDHC peripheral clock support had an
obvious error as below. This patch is used to fix it.

+#define define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK

Fixes: 3285e6cb ("powerpc/t2080qds: enable eSDHC peripheral clock support")
Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Fix the following warning on aarch64 introduced by using p2v/v2p
functions in the code:

In file included from ./arch/arm/include/asm/byteorder.h:29:0,
                 from include/compiler.h:125,
                 from include/image.h:19,
                 from include/common.h:88,
                 from drivers/usb/host/ehci-hcd.c:10:
drivers/usb/host/ehci-hcd.c: In function ‘ehci_td_buffer’:
drivers/usb/host/ehci-hcd.c:250:49: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
   td->qt_buffer[idx] = cpu_to_hc32(virt_to_phys((void *)addr));
                                                 ^
include/linux/byteorder/little_endian.h:34:51: note: in definition of macro ‘__cpu_to_le32’
 #define __cpu_to_le32(x) ((__force __le32)(__u32)(x))
                                                   ^
drivers/usb/host/ehci-hcd.c:250:24: note: in expansion of macro ‘cpu_to_hc32’
   td->qt_buffer[idx] = cpu_to_hc32(virt_to_phys((void *)addr));
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Tom Rini <trini@konsulko.com>

Fix the following compiler warnings when DEBUG is on.

warning: 'bar_res' may be used uninitialized in this function.
drivers/pci/pci_auto.c:101:21:
   if (!enum_only && pciauto_region_allocate(bar_res, bar_size,
                        ^
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

These are working correctly again, so re-enable them.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NJagan Teki <jteki@openedev.com>
Tested-by: NJagan Teki <jteki@openedev.com>

When an error number is provided we should use it, not change it. This fixes
the SPI and SPI flash tests.

One of these is long-standing. The other seems to have been introduced by
commit 1e90d9fd (sf: Move read_id code to sf_ops).
Signed-off-by: NSimon Glass <sjg@chromium.org>
Fixes: 1e90d9fd (sf: Move read_id code to sf_ops)
Reviewed-by: NJagan Teki <jteki@openedev.com>
Tested-by: NJagan Teki <jteki@openedev.com>

We must not free data that is managed by driver mode. Remove this line,
which is a hangover from the pre-driver-model code.

This fixes a problem where 'sf probe' crashes U-Boot if the backing file
for the SPI flash cannot be found.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NJagan Teki <jteki@openedev.com>
Tested-by: NJagan Teki <jteki@openedev.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Add a little more debugging to help when things go wrong.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NJagan Teki <jteki@openedev.com>
Tested-by: NJagan Teki <jteki@openedev.com>

Enable this so that tracing works with sandbox.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

This has got out of order: fix it.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add support for the early timer so we can use tracing with sandbox again.
Signed-off-by: NSimon Glass <sjg@chromium.org>

When using the early timer, we need to manually trigger setting up the
real timer. This will not happen automatically. Do this immediately after
starting driver model.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>