The NOR flash related configure options appear in ls2080aqds.h and
ls2080ardb.h, and the two files both includ ls2080a_common.h.
This patch remove the duplicated options in ls2080a_common.h.
Signed-off-by: NYuan Yao <yao.yuan@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Add early i2c init function with conservative divider when the exact
clock rate is not available.
Signed-off-by: NYuan Yao <yao.yuan@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

In the draco CPU board family, etamin is a new variant
with bigger flash and more RAM. Due to new flash that
uses larger pages (4K) some changes are necessary because
it impacts the MTD partition layout and the ubi mount
parameters.
Signed-off-by: NSamuel Egli <samuel.egli@siemens.com>
Signed-off-by: NHeiko Schocher <hs@denx.de>
[trini: Move BOOTDELAY into defconfig, just always be 3 now]
Signed-off-by: NTom Rini <trini@konsulko.com>

From: Samuel Egli <samuel.egli@siemens.com>
Signed-off-by: NHeiko Schocher <hs@denx.de>

U-Boot SPL 2016.03-rc3-00019-g6dfb4c2-dirty (Mar 09 2016 - 07:40:06)
SHC C3-Sample
MPU reference clock runs at 6 MHz
Setting MPU clock to 594 MHz
Enabling Spread Spectrum of 18 permille for MPU
Trying to boot from MMC
reading u-boot.img
reading u-boot.img

U-Boot 2016.03-rc3-00019-g6dfb4c2-dirty (Mar 09 2016 - 07:05:35 +0100)

       Watchdog enabled
I2C:   ready
DRAM:  512 MiB
reloc off 1f783000
MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
Net:   cpsw
U-Boot#
Signed-off-by: NHeiko Schocher <hs@denx.de>

show_boot_progress() is now called from SPL also.
Signed-off-by: NHeiko Schocher <hs@denx.de>

add the following defines, needed for the upcoming shc board
support:
Signed-off-by: NHeiko Schocher <hs@denx.de>
Reviewed-by: NTom Rini <trini@konsulko.com>

move CONFIG_BOOTDELAY into a Kconfig option. Used for this
purpose the moveconfig.py tool in tools.
Signed-off-by: NHeiko Schocher <hs@denx.de>
Reviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Acked-by: NIgor Grinberg <grinberg@compulab.co.il>

Unlike NAND, eMMC can be re-written without erasing.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The Boot ROM on PH1-LD11/LD20 exports built-in APIs to load images
from an eMMC device.  They are useful to reduce the memory footprint
of SPL, rather than compiling the whole MMC framework.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Avoid use of hard coded mmcdev value, use bootpart
instead, so finduuid works based on bootpart set
for a specific platform.
Signed-off-by: NRavi Babu <ravibabu@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Since bcopy() is no longer used, delete all remaining references to
it.
Signed-off-by: NRobert P. J. Day <rpjday@crashcourse.ca>

Now that all Keystone2 dts file names are changed in Linux kernel, reflect the
same in evn variables inorder to find the right dtb file.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

We introduced special "DEBUG_EFI" defines when the efi loader
support was new. After giving it a bit of thought, turns out
we really didn't have to - the normal #define DEBUG infrastructure
works well enough for efi loader as well.

So this patch switches to the common debug() and #define DEBUG
way of printing debug information.
Signed-off-by: NAlexander Graf <agraf@suse.de>

Some times you may want to exit an EFI payload again, for example
to default boot into a PXE installation and decide that you would
rather want to boot from the local disk instead.

This patch adds exit functionality to the EFI implementation, allowing
EFI payloads to exit.
Signed-off-by: NAlexander Graf <agraf@suse.de>

There is new strider cpu flavor with DisplayPort video.
Signed-off-by: NDirk Eibach <dirk.eibach@gdsys.cc>
Reviewed-by: NTom Rini <trini@konsulko.com>

There is a new strider console flavor with DisplayPort
video.
Signed-off-by: NDirk Eibach <dirk.eibach@gdsys.cc>
Reviewed-by: NTom Rini <trini@konsulko.com>

Nand and QSPI are not defined now but this will be extended.
Based on selected bootmode boot_targets are rewritten.
Patch also contains detection if variables are saved. If yes don't
rewrite boot_targets variable.

Also move variable setup to the end of file because SCSI needs to be
defined before others macros are using it.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NAlexander Graf <agraf@suse.de>

When the CONFIG_BOOTP_SERVERIP option is set, we ignore all
dhcp values for the tftp server and use our own serverip and
file name instead.

This is usually not what we want and I doubt it's set for a
good reason on ZynqMP. It definitely hurts if we want to support
uEFI PXE boot on it. So just remove the option for now.
Signed-off-by: NAlexander Graf <agraf@suse.de>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Simplify zcu102 board file by moving CONFIG_AHCI enabling to common
file.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Setup flag when default environment are used to be able to
rewrite default distro boot variables based on SoC boot mode.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NAlexander Graf <agraf@suse.de>

zc1751-dc4 contains four GEMs.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Phys are available on zc1751-dc4 that's why enable them.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Simplify board file by enabling CMD_NAND via Kconfig.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Certain GPIO devices have the capability to switch their GPIOs into
open-drain mode, that is, instead of actively driving the output
(Push-pull output), the pin is connected to the collector (for a NPN
transistor) or the drain (for a MOSFET) of a transistor, respectively.
The pin then either forms an open circuit or a connection to ground,
depending on the state of the transistor.

This patch adds functions to the GPIO uclass to switch GPIOs to
open-drain mode on devices that support it.
Signed-off-by: NMario Six <mario.six@gdsys.cc>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Updates the NAND code to match Linux v4.6.  The previous sync was from
Linux v4.1 in commit d3963721.

Note that none of the individual NAND drivers tracked Linux closely
enough to be synced themselves, other than manually applying a few
cross-tree changes.
Signed-off-by: NScott Wood <oss@buserror.net>
Tested-by: NHeiko Schocher <hs@denx.de>

This change is part of the Linux 4.6 sync.  It is being done before the
main sync patch in order to make it easier to address the issue across
all NAND drivers (many/most of which do not closely track their Linux
counterparts) separately from other merge issues.
Signed-off-by: NScott Wood <oss@buserror.net>

These functions are part of the Linux 4.6 sync.  They are being added
before the main sync patch in order to make it easier to address the
issue across all NAND drivers (many/most of which do not closely track
their Linux counterparts) separately from other merge issues.
Signed-off-by: NScott Wood <oss@buserror.net>

nand_info[] is now an array of pointers, with the actual mtd_info
instance embedded in struct nand_chip.

This is in preparation for syncing the NAND code with Linux 4.6,
which makes the same change to struct nand_chip.  It's in a separate
commit due to the large amount of changes required to accommodate the
change to nand_info[].
Signed-off-by: NScott Wood <oss@buserror.net>

This typedef serves no purpose other than causing confusion with
struct nand_chip.
Signed-off-by: NScott Wood <oss@buserror.net>

Commit ad4f54ea ("arm: Remove palmtreo680 board") removed the only
user of the docg4 driver and the palmtreo680 image flashing tool.  This
patch removes them.
Signed-off-by: NScott Wood <oss@buserror.net>
Cc: Mike Dunn <mikedunn@newsguy.com>
Cc: Simon Glass <sjg@chromium.org>

Create an entry for "config USB_XHCI_DWC3" in Kconfig and
switch over to it for all boards.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Move CONFIG_USB_XHCI to defconfig files for all boards, renaming it
into CONFIG_USB_XHCI_HCD.

As commented in the help of "config USB_XHCI" entry, this has been
a TODO for a long time; now CONFIG_USB_XHCI_HCD and CONFIG_USB_XHCI
have been unified in favor of the former.

Note:
Some boards define CONFIG_USB_XHCI in their headers without
CONFIG_USB, which does not meet the "depends on" in Kconfig.
I added CONFIG_USB=y for those boards when converting.
Otherwise, they would fail to build.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

These Blackfin boards are the last ones that define CONFIG_USB in
their headers.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Correct type of varibale base to unsigned long as
keeping it as int causes usb failures if MSB of
the base address is set.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance
development platform, with a complete debugging environment.
The LS1012AFRDM board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@nxp.com>
Signed-off-by: NCalvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: NPratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
Signed-off-by: NCalvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: NPratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
development platform, with a complete debugging environment.
The LS1012AQDS board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
Signed-off-by: NCalvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: NPratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: NAbhimanyu Saini <abhimanyu.saini@nxp.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.

This patch add support of LS1012A SoC along with
 - Update platform & DDR clock read logic as per SVR
 - Define MMDC controller register set.
 - Update LUT base address for PCIe
 - Avoid L3 platform cache compilation
 - Update USB address, errata
 - SerDes table
 - Added CSU IDs for SDHC2, SAI-1 to SAI-4
Signed-off-by: NCalvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: NMakarand Pawagi <makarand.pawagi@mindspeed.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This fixes the last remaining libgcc warning, where the symbol was
defined twice.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: NTom Rini <trini@konsulko.com>