- 25 5月, 2021 9 次提交
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由 Marek Behún 提交于
Document the macros __efi_runtime and __efi_runtime_data in Sphinx style. Signed-off-by: NMarek Behún <marek.behun@nic.cz> Reviewed-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
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由 Marek Behún 提交于
When linking with LTO, the compiler complains about type mismatch of variables `__efi_runtime_start`, `__efi_runtime_stop`, `__efi_runtime_rel_start` and `__efi_runtime_rel_stop`: include/efi_loader.h:218:21: warning: type of ‘__efi_runtime_start’ does not match original declaration [-Wlto-type-mismatch] 218 | extern unsigned int __efi_runtime_start, __efi_runtime_stop; | ^ arch/sandbox/lib/sections.c:7:6: note: ‘__efi_runtime_start’ was previously declared here 7 | char __efi_runtime_start[0] __attribute__((section(".__efi_run | ^ Change the type to char[] in include/efi_loader.h. Signed-off-by: NMarek Behún <marek.behun@nic.cz> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Marek Behún 提交于
It seems that sometimes (happening on ARM64, for example with turris_mox_defconfig) GCC, when linking with LTO, changes the symbol names of some functions, for example lib/string.c's memcpy() function to memcpy.isra.0. This is a problem however when GCC for a code such as this: struct some_struct *info = get_some_struct(); struct some struct tmpinfo; tmpinfo = *info; emits a call to memcpy() by builtin behaviour, to copy *info to tmpinfo. This then results in the following linking error: .../lz4.c:93: undefined reference to `memcpy' .../uuid.c:206: more undefined references to `memcpy' follow GCC's documentation says this about -nodefaultlibs option: The compiler may generate calls to "memcmp", "memset", "memcpy" and "memmove". These entries are usually resolved by entries in libc. These entry points should be supplied through some other mechanism when this option is specified. Make these functions visible by using the __used macro to avoid this error. Signed-off-by: NMarek Behún <marek.behun@nic.cz> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Marek Behún 提交于
Improve the regular expression that matches unittest symbols in u-boot.sym. Currently we do not enforce no prefix in symbol string, but with the soon to come change in linker lists declaring lists and entries with the __ADDRESSABLE macro (because of LTO), the symbol file will contain for every symbol of the form _u_boot_list_2_ut_X_2_Y also symbol __UNIQUE_ID___addressable__u_boot_list_2_ut_X_2_YN, (where N at the end is some number). In order to avoid matching these additional symbols, ensure that the character before "_u_boot_list_2_ut" is not a symbol name character. Signed-off-by: NMarek Behún <marek.behun@nic.cz> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Marek Behún 提交于
Use UNIQUE_ID in the __ADDRESSABLE macro. Signed-off-by: NMarek Behún <marek.behun@nic.cz> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Marek Behún 提交于
This commit does the same thing as Linux commit 33def8498fdd. Use a more generic form for __section that requires quotes to avoid complications with clang and gcc differences. Remove the quote operator # from compiler_attributes.h __section macro. Convert all unquoted __section(foo) uses to quoted __section("foo"). Also convert __attribute__((section("foo"))) uses to __section("foo") even if the __attribute__ has multiple list entry forms. Signed-off-by: NMarek Behún <marek.behun@nic.cz> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Marek Behún 提交于
This is how Linux does this now, see Linux commit 339f29d91acf. Signed-off-by: NMarek Behún <marek.behun@nic.cz> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Marek Behún 提交于
There is a serious bug in regmap_read() and regmap_write() functions where an uint pointer is cast to (void *) which is then cast to (u8 *), (u16 *), (u32 *) or (u64 *), depending on register width of the map. For example given a regmap with 16-bit register width the code int val = 0x12340000; regmap_read(map, 0, &val); only changes the lower 16 bits of val on little-endian machines. The upper 16 bits will remain 0x1234. Nobody noticed this probably because this bug can be triggered with regmap_write() only on big-endian architectures (which are not used by many people anymore), and on little endian this bug has consequences only if register width is 8 or 16 bits and also the memory place to which regmap_read() should store it's result has non-zero upper bits, which it seems doesn't happen anywhere in U-Boot normally. CI managed to trigger this bug in unit test of dm_test_devm_regmap_field when compiled for sandbox_defconfig using LTO. Fix this by utilizing an union { u8; u16; u32; u64; } and reading data into this union / writing data from this union. Signed-off-by: NMarek Behún <marek.behun@nic.cz> Cc: Simon Glass <sjg@chromium.org> Cc: Heiko Schocher <hs@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Pratyush Yadav <p.yadav@ti.com>
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由 Simon Glass 提交于
There is no good reason to use a sequence from rand() here. We may as well invent our own sequence. This should molify Coverity which does not use rand() being used. Signed-off-by: NSimon Glass <sjg@chromium.org> Reported-by: Coverity (CID: 312949)
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- 24 5月, 2021 1 次提交
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由 Tom Rini 提交于
Clang has -Wself-assign enabled by default under -Wall and so when building with -Werror we would get an error here. Inspired by Linux kernel git commit a21151b9d81a ("tools/build: tweak unused value workaround") make use of the fact that both Clang and GCC support casting to `void` as the method to note that something is intentionally unused. Signed-off-by: NTom Rini <trini@konsulko.com>
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- 23 5月, 2021 1 次提交
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https://source.denx.de/u-boot/custodians/u-boot-sh由 Tom Rini 提交于
- Various clk/pinctrl updates to re-sync with Linux and other fixes
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- 21 5月, 2021 16 次提交
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由 Marek Vasut 提交于
The V3U SoC has several unlock registers, one per register group. They reside at offset zero in each 0x200 bytes-sized block. To avoid adding yet another table to the PFC implementation, this patch adds the option to specify an address mask instead of the fixed address in sh_pfc_soc_info::unlock_reg. This is a direct port of Linux 5.12 commit e127ef2ed0a6 ("pinctrl: renesas: Implement unlock register masks") by Ulrich Hecht <uli+renesas@fpond.eu> Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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由 Marek Vasut 提交于
The help text for Gen2 entries had a copy paste error, still containing the Gen3 string, while the description was correctly listing Gen2. Fix the help text. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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由 Marek Vasut 提交于
The help text in the Kconfig file was always a copy of the same thing. Move single copy into the common PFC driver entry instead. Also fix a copy-paste error in the PFC help text, which identified PFC as clock. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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由 Marek Vasut 提交于
Pass struct udevice to rcar_gpio_set_direction() in preparation of quirk handling in rcar_gpio_set_direction(). No functional change. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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由 Marek Vasut 提交于
Most of the PLLx, MAIN, FIXED clock handlers are calling very similar code, which determines parent rate and then applies multiplication and division. The only difference is whether multiplication is fixed factor or coming from CRx register. Deduplicate the code into a single function. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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由 Hai Pham 提交于
Base on Linux v5.10-rc2, commit 8b652aa8a1fb by Yoshihiro Shimoda To support other register layouts in the future, add register pointers of {control,status,reset,reset_clear}_regs into struct cpg_mssr_info Signed-off-by: NHai Pham <hai.pham.ud@renesas.com> Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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由 Hai Pham 提交于
From Linux v5.10-rc2, commit ffbf9cf3f946 by Yoshihiro Shimoda Introduce enum clk_reg_layout to support multiple register layout variants Signed-off-by: NHai Pham <hai.pham.ud@renesas.com> Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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由 Hai Pham 提交于
CPG IP in some specific Renesas SoCs (i.e. new R8A779A0 V3U SoC) requires a different setting procedure. Make struct cpg_mssr_info accessible to handle the clock setting in that case. Signed-off-by: NHai Pham <hai.pham.ud@renesas.com> Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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由 Marek Vasut 提交于
The MODEMR register offset changed on R8A779A0, make the MODEMR offset configurable. Fill the offset in on all clock drivers. No functional change. Based off "clk: renesas: Make CPG Reset MODEMR offset accessible from struct cpg_mssr_info" by Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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由 Hai Pham 提交于
This supports RPCD2 clock handling. While at it, add the check point for RPC-IF clock RPCD2 Frequency Division Ratio, since it must be odd number Signed-off-by: NHai Pham <hai.pham.ud@renesas.com> Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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由 Hai Pham 提交于
This patch fixes Realtime Module Stop Control Register (RMSTPCR) offsets based on R-Car Gen3, H2/M2/M2N/E2/E2X hardware user's manual. The r8a73a4 only has RMSTPCR0 - RMSTPCR5 so this calculation change doesn't affect it. Signed-off-by: NHai Pham <hai.pham.ud@renesas.com> Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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由 Hai Pham 提交于
RPC clk_get_rate will return error code instead of expected clock rate. Fix this. Signed-off-by: NHai Pham <hai.pham.ud@renesas.com> Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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由 Marek Vasut 提交于
Reinstate RPC clock on D3/E3 after Linux 5.12 synchronization. The D3 and E3 clock drivers do not contain RPC clock entries mainline Linux yet. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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由 Marek Vasut 提交于
Synchronize R-Car Gen3 clock tables with Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") . Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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由 Marek Vasut 提交于
Synchronize R-Car Gen2 clock tables with Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") . Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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由 Marek Vasut 提交于
Synchronize RZ/G2 clock tables with Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") . Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
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- 20 5月, 2021 13 次提交
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https://source.denx.de/u-boot/custodians/u-boot-marvell由 Tom Rini 提交于
- Sync Armada mvpp2 ethernet driver with Marvell version (misc Marvell authors)
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由 Stefan Roese 提交于
With commit 8678776d (arm: mvebu: armada-3720-uDPU: fix PHY mode definition to sgmii-2500) the PHY mode was switch to "sgmii-2500", even when this is functionally incorrect since "2500base-x" was not supported in U-Boot at that time. As this mode is now supported (at least present in the headers), this patch moves back to the orinal version. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Jakov Petrina <jakov.petrina@sartura.hr> Cc: Vladimir Vid <vladimir.vid@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
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由 Marcin Wojtas 提交于
Until now the mvpp2 driver used an extra 'phy-speed' DT property in order to differentiate between the SGMII and SGMII @2.5GHz. As there is a dedicated PHY_INTERFACE_MODE_SGMII_2500 flag to mark the latter start using it and drop the custom flag. Signed-off-by: NMarcin Wojtas <mw@semihalf.com> Reviewed-by: NStefan Chulski <stefanc@marvell.com> Reviewed-by: NNadav Haklai <nadavh@marvell.com> Tested-by: NNadav Haklai <nadavh@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de> Reviewed-by: NRamon Fried <rfried.dev@gmail.com>
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由 Stefan Chulski 提交于
Currently, there are 2 valid cases for interface, PHY and mdio relation: - If an interface has PHY handler, it'll call mdio_mii_bus_get_from_phy(), which will register MDIO bus. - If we want to use fixed-link for an interface, PHY handle is not defined in the DTS, and no MDIO is registered. There is a third case, for some boards (with switch), the MDIO is used for switch configuration, but the interface itself uses fixed link. This patch allows this option by checking if fixed-link subnode is defined, in this case, MDIO bus is registers, but the PHY address is set to PHY_MAX_ADDR for this interface, so this interface will not try to access the PHY later on. Signed-off-by: NStefan Chulski <stefanc@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Ben Peled 提交于
Signed-off-by: NBen Peled <bpeled@marvell.com> Reviewed-by: NStefan Chulski <stefanc@marvell.com> Reviewed-by: NKostya Porotchkin <kostap@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de> Reviewed-by: NRamon Fried <rfried.dev@gmail.com>
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由 Ben Peled 提交于
Signed-off-by: NBen Peled <bpeled@marvell.com> Reviewed-by: NStefan Chulski <stefanc@marvell.com> Reviewed-by: NKostya Porotchkin <kostap@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de> Reviewed-by: NRamon Fried <rfried.dev@gmail.com>
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由 Ben Peled 提交于
Signed-off-by: NBen Peled <bpeled@marvell.com> Reviewed-by: NStefan Chulski <stefanc@marvell.com> Reviewed-by: NKostya Porotchkin <kostap@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Chulski 提交于
GMII_SPEED should be enabled for 2.5G speed Signed-off-by: NStefan Chulski <stefanc@marvell.com> Reviewed-by: NYan Markman <ymarkman@marvell.com> Reviewed-by: NKostya Porotchkin <kostap@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Marcin Wojtas 提交于
Because the mvpp2 driver now relies on the PHYLIB and the external MDIO driver, configuring low level SMI bus settings is redundant. Signed-off-by: NMarcin Wojtas <mw@semihalf.com> Reviewed-by: NKostya Porotchkin <kostap@marvell.com> Reviewed-by: NStefan Chulski <stefanc@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de> Reviewed-by: NRamon Fried <rfried.dev@gmail.com>
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由 Stefan Chulski 提交于
Signed-off-by: NStefan Chulski <stefanc@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de> Reviewed-by: NRamon Fried <rfried.dev@gmail.com>
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由 Stefan Chulski 提交于
1. Differ between Port1 RGMII and SFI modes in Netcomplex config. 2. Remove XPCS config from SFI mode. Port1 doesn't XPCS domain, XPCS config should be removed. Access to Port1 XPCS can cause stall. 3. Add Port1 MPCS configurations. Signed-off-by: NStefan Chulski <stefanc@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Chulski 提交于
Signed-off-by: NStefan Chulski <stefanc@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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