- 12 12月, 2016 6 次提交
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由 Konstantin Porotchkin 提交于
Enable mvebu pin control support in the default configuration files for Armada-7040 and Armada-8040 development boards Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Konstantin Porotchkin 提交于
Enable mvebu "bubt" command support in the default configuration file for Armada-7040 and Armada-8040 development boards Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Konstantin Porotchkin 提交于
Add pin control nodes to APN806, CP-master, CP-slave and Armada-7040 and Armada-8040 boards DTS files Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Konstantin Porotchkin 提交于
Add a DM port of Marvell pin control driver. The A8K SoC family contains several silicone dies interconnected in a single package. Every die is normally equipped with its own pin controller unit. There are 2 pin controllers in A70x0 SoC and 3 in A80x0 SoC. Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Konstantin Porotchkin 提交于
Add support for mvebu bubt command for flash image load, check and burn on boot device. Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Reviewed-by: NStefan Roese <sr@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Konstantin Porotchkin 提交于
Align the Armada-8040-db and Armada-7040-db SPI and I2C DTS settings with latest DB settings: - 8040-db: disable i2c0 and spi0 on AP (MPPs are reserved for SDIO) - 8040-db: disable cps_i2c0 on CP1 - 8040-db: enable spi1 on CP1 (the new location of the boot flash) The spi1 on CP1 is aliased as spi0 since this is the way the driver enumerates it. Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com> Reviewed-by: NStefan Roese <sr@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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- 09 12月, 2016 9 次提交
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git://www.denx.de/git/u-boot-microblaze由 Tom Rini 提交于
This reverts commit 3edc0c25, reversing changes made to bb135a01.
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由 Alex 提交于
The VSC8601 config tried to add an RGMII skew based on #defines that no config defines. That's quite an ugly way to do it. Since the skew is only needed on RGMII interfaces, check the interface mode at runtime, and apply the settings accordingly. Tested on custom board with AM3352 SOC and VSC801 PHY. Signed-off-by: NAlexandru Gagniuc <alex.g@adaptrum.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Stefan Roese 提交于
Testing on theadorable (Armada XP) has shown, that using this driver results in many cache misaligned warning, such as: CACHE: Misaligned operation at range [7fabd8fc, 7fabd900] This patch now uses the ALLOC_CACHE_ALIGN_BUFFER() macro to allocate the buffers on a cache aligned boundary. This fixes all warnings seen on the Armada XP platform. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Ted Chen <tedchen@realtek.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 shaohui xie 提交于
The settings for 2.5G SGMII are wrong, which the 2.5G case is missed in set_if_mode(), and the serdes PCS configuration are wrong, this patch uses the correct settings took from Linux. Signed-off-by: NShaohui Xie <Shaohui.Xie@nxp.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 oliver@schinagl.nl 提交于
Commit 525d187a ("net: phy: Optionally force master mode for RTL PHY") added the define to force the PHY into master mode. Unfortunatly this is an all or nothing switch. So it applies to either all PHY's or no PHY's. The bug that define tried to solve was a buggy PLL in the RTL8211C only. The Olimex OLinuXino Lime2 has gotten an upgrade where the PHY was replaced with an RTL8211E. With this define however, both lime2 boards are either forced to master mode or not. We could of course have a binary for each board, but the following patch fixes this by adding a 'quirk' to the flags to the rtl8211b and rtl8211c only. It is now possible to force master mode, but only have it apply to the rtl8211b and rtl8211c. Signed-off-by: NOlliver Schinagl <oliver@schinagl.nl> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 oliver@schinagl.nl 提交于
All internal defines in the realtek phy are with a small X, except MIIM_RTL8211X_CTRL1000T_MASTER. Make this more consistent Signed-off-by: NOlliver Schinagl <oliver@schinagl.nl> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 oliver@schinagl.nl 提交于
The BIT macro is the preferred method to set bits. This patch adds the bit macro and converts bit invocations. Signed-off-by: NOlliver Schinagl <oliver@schinagl.nl> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Marek Vasut 提交于
Fix the following error, the $ret variable handling must be part of the loop, while due to the missing parenthesis it was not. drivers/net/phy/micrel.c: In function ‘ksz9021_of_config’: drivers/net/phy/micrel.c:303:2: warning: this ‘for’ clause does not guard... [-Wmisleading-indentation] for (i = 0; i < ARRAY_SIZE(ofcfg); i++) ^~~ drivers/net/phy/micrel.c:305:3: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the ‘for’ if (ret) ^~ drivers/net/phy/micrel.c: In function ‘ksz9031_of_config’: drivers/net/phy/micrel.c:411:2: warning: this ‘for’ clause does not guard... [-Wmisleading-indentation] for (i = 0; i < ARRAY_SIZE(ofcfg); i++) ^~~ drivers/net/phy/micrel.c:413:3: note: ...this statement, but the latter is misleadingly indented as if it is guarded by the ‘for’ if (ret) ^~ Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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- 08 12月, 2016 9 次提交
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由 Michal Simek 提交于
axi_emac, emaclite and gem have the same issue with registering multiple instances with mdio busses. mdio bus name has to be uniq but drivers are setting up only one name for all. Use mdio_register_seq() and pass dev->seq number to allow multiple mdio instances registration. Reported-by: NPhani Kiran Kara <phanikiran.kara@gmail.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Series-to: u-boot Series-cc: Phani Kiran Kara <phanikiran.kara@gmail.com>
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由 Michal Simek 提交于
The most of ethernet drivers are using this mdio registration sequence. strcpy(priv->bus->name, "emac"); mdio_register(priv->bus); Where driver can be used only with one MDIO bus because only unique name should be used. Other drivers are using unique device name for MDIO registration to support multiple instances. snprintf(priv->bus->name, sizeof(bus->name), "%s", name); With DM dev->seq is used more even in logs (like random MAC address generation: printf("\nWarning: %s (eth%d) using random MAC address - %pM\n", dev->name, dev->seq, pdata->enetaddr); ) where eth%d prefix is used. Simplify driver code to register mdio device with dev->seq number to simplify mdio registration and reduce code duplication across all drivers. With DM_SEQ_ALIAS enabled dev->seq reflects alias setting. Signed-off-by: NMichal Simek <michal.simek@xilinx.com> --- For example: Board: Xilinx Zynq Net: ZYNQ GEM: e000b000, phyaddr 7, interface rgmii-id Warning: ethernet@e000b000 (eth0) using random MAC address - 7a:fc:90:53:6a:41 eth0: ethernet@e000b000ZYNQ GEM: e000c000, phyaddr ffffffff, interface rgmii-id Warning: ethernet@e000c000 (eth3) using random MAC address - 1a:ff:d7:1a:a1:b2 , eth3: ethernet@e000c000 ** Bad device size - mmc 0 ** Checking if uenvcmd is set ... Hit any key to stop autoboot: 0 Zynq> mdio list eth0: 17 - Marvell 88E1111S <--> ethernet@e000b000 eth3: 17 - Marvell 88E1111S <--> ethernet@e000c000 Zynq>
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由 Michal Simek 提交于
With origin files there was an issue with serdes setting for SCSI. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
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由 Nathan Rossi 提交于
The dram_init* functions for the zynq board are not safe for use from the board_init_f stage due to its use of the 'tmp' static variable. This incorrect use of a static variable was causing rare issues where the dram_init function would overwrite some parts the __rel_dyn section which caused obscure failures. Using the zynq_zybo configuration, U-Boot would generate the following error during image load. This was caused due to dram_init overwriting the relocations for the "image" variable within the do_bootm function. Out of coincidence the un-initialized memory has a compression type which is the same as the value for the relocation type R_ARM_RELATIVE. Uncompressing Invalid Image ... Unimplemented compression type 23 It should be noted that this is just one way the issue could surface, other cases my not be observed in normal boot flow. This change removes the existing code and copies the implementation of the dram_init and dram_init_banksize from the arch/arm/mach-uniphier/dram_init.c source. This version of these functions does not use static variables and behaves the same (reading banks from fdt, and using the first bank as the ram_size). Signed-off-by: NNathan Rossi <nathan@nathanrossi.com> Fixes: 758f29d0 ("ARM: zynq: Support systems with more memory banks") Cc: Michal Simek <monstr@monstr.eu> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Use embded option because of qemu Use my repo till Stephen merge it. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
The patch is fixing: "tools: mkimage: Check if file is regular file" (sha1: 56c7e801) which contains two issues reported by Coverity Unchecked return value from stat and incorrect calling sequence where attack can happen between calling stat and fopen. Using pair in opposite order (fopen and fstat) is fixing this issue because fstat is using the same file descriptor (FILE *). Also fixing issue with: "tools: mkimage: Add support for initialization table for Zynq and ZynqMP" (sha1: 3b646080) where file wasn't checked that it is regular file. Reported-by: Coverity (CID: 154711, 154712) Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Reviewed-by: NTom Rini <trini@konsulko.com> Series-to: trini Series-cc: u-boot
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由 Michal Simek 提交于
This patch also includes ARM64 zynqmp changes: - Remove platform non DM initialization - Remove hardcoded sata base address Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Series-to: sjg, agraf@suse.de Series-cc: uboot Series-version: 4 Series-changes: 2 - make ceva_init_sata static - Move SATA_CEVA to defconfig - Initalized max_lun and max_id platdata Series-changes: 3 - Extend Kconfig help description - sort dm.h - Remove SPL undefinition from board file - Fix Kconfig dependecies
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由 Michal Simek 提交于
All sata based drivers are bind and corresponding block device is created. Based on this find_scsi_device() is able to get back block device based on scsi_curr_dev pointer. intr_scsi() is commented now but it can be replaced by calling find_scsi_device() and scsi_scan(). scsi_dev_desc[] is commented out but common/scsi.c heavily depends on it. That's why CONFIG_SYS_SCSI_MAX_DEVICE is hardcoded to 1 and symbol is reassigned to a block description allocated by uclass. There is only one block description by device now but it doesn't need to be correct when more devices are present. scsi_bind() ensures corresponding block device creation. uclass post_probe (scsi_post_probe()) is doing low level init. SCSI/SATA DM based drivers requires to have 64bit base address as the first entry in platform data structure to setup mmio_base. Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Series-changes: 2 - Use CONFIG_DM_SCSI instead of mix of DM_SCSI and DM_SATA Ceva sata has never used sata commands that's why keep it in SCSI part only. - Separate scsi_scan() for DM_SCSI and do not change cmd/scsi.c - Extend platdata Series-changes: 3 - Fix scsi_scan return path - Fix header location uclass-internal.h - Add scsi_max_devs under !DM_SCSI - Add new header device-internal because of device_probe() - Redesign block device creation algorithm - Use device_unbind in error path - Create block device with id and lun numbers (lun was there in v2) - Cleanup dev_num initialization in block device description with fixing parameters in blk_create_devicef - Create new Kconfig menu for SATA/SCSI drivers - Extend description for DM_SCSI - Fix Kconfig dependencies - Fix kernel doc format in scsi_platdata - Fix ahci_init_one - vendor variable Series-changes: 4 - Fix Kconfig entry - Remove SPL ifdef around SCSI uclass - Clean ahci_print_info() ifdef logic
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- 06 12月, 2016 16 次提交
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由 Stefan Roese 提交于
This patch adds DM support to the xHCI PCI driver. Enabling its use e.g. in x86 platforms. Status: On the congatec BayTrail SoM, xHCI still does not work correctly with this patch. Some internal timeouts lead to resets (BUG). Additional work is needed here. I'm posting this version as WIP so that other developers interested in this support might use it as a start. I might get back to it in a few weeks as well. Signed-off-by: NStefan Roese <sr@denx.de> Cc: George McCollister <george.mccollister@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Jagan Teki 提交于
Replace arch/arm/cpu/armv7/socfpga/ path with arch/arm/mach-socfpga/ and removed board file path since board/altera has different boards with relevant board maintainers. Cc: Marek Vasut <marex@denx.de> Signed-off-by: NJagan Teki <jagan@openedev.com>
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由 Dinh Nguyen 提交于
With the acquisition of Altera by Intel, my Altera email may be going away soon. Update the contact to a more reliable address. Signed-off-by: NDinh Nguyen <dinguyen@kernel.org>
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由 Bill Randle 提交于
Some Altera Quartus generated files have long lines that are split with a '\' at the end of the line. It also wOn Windows, rites files in DOS format, which can confuse some of the processing scripts in this file. This patch solves both issues. Signed-off-by: NBill Randle <bill.randle@gmail.com> Cc: Marek Vasut <marex@denx.de>
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由 Marek Vasut 提交于
Valid Altera SoCFPGA preloader image must contain special data at offsets 0x40, 0x44, 0x48 and valid instructions at address 0x4c or 0x50. These addresses are by default used by U-Boot's vector table and a piece of reset handler, thus a valid preloader corrupts those addresses slightly. While this works most of the time, this can and does prevent the board from rebooting sometimes and triggering this issue may even depend on compiler. The problem is that when SoCFPGA performs warm reset, it checks the addresses 0x40..0x4b in SRAM for a valid preloader signature and header checksum. If those are found, it jumps to address 0x4c or 0x50 (this is unclear). These addresses are populated by the first few instructions of arch/arm/cpu/armv7/start.S: ffff0040 <data_abort>: ffff0040: ebfffffe bl ffff0040 <data_abort> ffff0044 <reset>: ffff0044: ea000012 b ffff0094 <save_boot_params> ffff0048 <save_boot_params_ret>: ffff0048: e10f0000 mrs r0, CPSR ffff004c: e200101f and r1, r0, #31 ffff0050: e331001a teq r1, #26 Without this patch, the CPU will enter the code at 0xffff004c or 0xffff0050 , at which point the value of r0 and r1 registers is undefined. Moreover, jumping directly to the preloader entry point at address 0xffff0000 will also fail, because address 0xffff004. is invalid and contains the preloader magic. Add BOOT0 hook which reserves the area at offset 0x40..0x5f and populates offset 0x50 with jump to the entry point. This way, the preloader signature is stored in reserved space and can not corrupt the SPL code. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Stefan Roese <sr@denx.de> Tested-by: NDinh Nguyen <dinguyen@opensource.altera.com>
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由 Anatolij Gustschin 提交于
Add CycloneV based Terasic DE1-SoC board. The board boots from SD/MMC. Ethernet and USB host is supported. Signed-off-by: NAnatolij Gustschin <agust@denx.de> Cc: Marek Vasut <marex@denx.de>
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由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Yuan Yao 提交于
The default configuration for QSPI AHB bus can't support 16MB+. But some flash on NXP layerscape board are more than 16MB. Signed-off-by: NYuan Yao <yao.yuan@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 jerry.huang@nxp.com 提交于
Enable the errata-a005697 for ls1012a Signed-off-by: NChangming Huang <jerry.huang@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Yuan Yao 提交于
Add the name for register space and memory space. <0x1550000 0x10000 > is the QSPI register space. <0x40000000 0x4000000> is the QSPI memory space. Signed-off-by: NYuan Yao <yao.yuan@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Priyanka Jain 提交于
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Shengzhou Liu 提交于
- add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Shengzhou Liu 提交于
Fix following warning in case multiple erratum macro was not defined. warning: unused variable 'tmp' warning: unused variable 'ddr_freq' Signed-off-by: NShengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Stefan Roese 提交于
Its easier to watch the output of the build process when the platforms specific boards are grouped in a separate job. This patch adds a job for all mvebu boards (arm and aarch64). Signed-off-by: NStefan Roese <sr@denx.de> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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