As 3G/1G user/kernel memory split is used on LS1021A, the Linux kernel
fails to access the device tree blob on boot. The reason is that u-boot
relocates the device tree blob into high memory when booting the kernel
and the kernel is unable to access the blob.

To avoid this issue, fdt_high is set to the value of 0xffffffff. The
device tree blob will not get relocated and is still in low memory to
make it accessible to the kernel.

For the same reason, initrd_high is set to the value of 0xffffffff too.
Signed-off-by: NAlison Wang <alison.wang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

After the secondary cores enter U-Boot, use CONFIG_ARMV8_MULTIENTRY to
make secondary cores excute in spin loop.
Signed-off-by: NHou Zhiqiang <B48286@freescale.com>
Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

This patch adds esdhc support for ls1043ardb.
Signed-off-by: NYangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Signed-off-by: NHou Zhiqiang <B48286@freescale.com>
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>
Signed-off-by: NHou Zhiqiang <B48286@freescale.com>
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

LS1043ARDB Specification:
-------------------------
Memory subsystem:
 * 2GByte DDR4 SDRAM (32bit bus)
 * 128 Mbyte NOR flash single-chip memory
 * 512 Mbyte NAND flash
 * 16 Mbyte high-speed SPI flash
 * SD connector to interface with the SD memory card

Ethernet:
 * XFI 10G port
 * QSGMII with 4x 1G ports
 * Two RGMII ports

PCIe:
 * PCIe2 (Lanes C) to mini-PCIe slot
 * PCIe3 (Lanes D) to PCIe slot

USB 3.0: two super speed USB 3.0 type A ports

UART: supports two UARTs up to 115200 bps for console
Signed-off-by: NHou Zhiqiang <B48286@freescale.com>
Signed-off-by: NLi Yang <leoli@freescale.com>
Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>

Freescale LayerScape with Chassis Generation 2 is a set of SoCs with
ARMv8 cores and 2rd generation of Chassis.
Signed-off-by: NLi Yang <leoli@freescale.com>
Signed-off-by: NHou Zhiqiang <B48286@freescale.com>
Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

There are two LS series processors are built on ARMv8 Layersacpe
architecture currently, LS2085A and LS1043A. They are based on
ARMv8 core although use different chassis, so create fsl-layerscape
to refactor the common code for the LS series processors which also
paves the way for adding LS1043A platform.
Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: NHou Zhiqiang <B48286@freescale.com>
Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

MDIO controller base on FMAN2 was defined as CONFIG_SYS_FSL_FM2_ADDR
plus offset, but CONFIG_SYS_FSL_FM2_ADDR only defined when there are two
FMANs, so we should only define MDIO controller base on FMAN2 when there
is FMAN2.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

QSGMII PCS needed to be programmed same as SGMII PCS, and there are
four ports in QSGMII PCS, port 0, 1, 2, 3, all the four ports shared
port 0's MDIO controller, so when programming port 0, we continue to
program other three ports.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM
and PPC, move it out of ppc to include/, and change the path in
drivers accordingly.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

codes related to phylib operations should be wrapped by CONFIG_PHYLIB.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

In convention, the '0' is a normal return value indicating there isn't
an error. While some functions of FMan IM driver treat '0' as an error
return value.
Signed-off-by: NHou Zhiqiang <B48286@freescale.com>
Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

The FMan IM driver is developed for 32-bit platfroms and isn't
friendly to 64-bit platforms, so do the minimal refactor:

1. Refine the MURAM management and access.
2. Correct the initialization and operations for QDs and BDs.
Signed-off-by: NHou Zhiqiang <B48286@freescale.com>
Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

The Frame Manager(FMan) is a big-endian peripheral, so the
registers, internal MURAM and BDs, which are allocated in main
memory and used to communication between core and FMan, should
be accessed in big-endian. The big-endian platforms can access
them directly as the code implemented so far, while for the
little-endian platforms it need to swap the byte-order.
Signed-off-by: NHou Zhiqiang <B48286@freescale.com>
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Config Security Level Register is different between different SoCs,
so put the CSL register definition into the arch specific directory.
Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: NHou Zhiqiang <B48286@freescale.com>
Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

For most PPC platforms, they will call the first get_clocks() in
init_sequence_f[] as they define CONFIG_PPC. CONFIG_SYS_FSL_CLK is
then defined to call the second get_clocks(), which should be
redundant for PPC.
Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Enable snooping for CAAM read & write transactions by
programming the SCFG snoop configuration register:
SCFG_SNPCNFGCR[SECRDSNP]
SCFG_SNPCNFGCR[SECWRSNP]
Signed-off-by: NHoria Geantă <horia.geanta@freescale.com>
Reviewed-by: NZhengxiong Jin <Jason.Jin@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Add support of setting RANDOM MAC address if env variable not available.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Currently ldpaa ethernet driver rely on DPL file to statically configure
mac address for the DPNIs. It is not a correct approach.

Add support setting MAC address from env variable or Random MAC address.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

To support on board Aquantia's PHY AQR405.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

The SEC driver code has been cleaned up to work for 64 bit
physical addresses and systems where endianess of SEC block
is different from the Core.
Changes:
1. Descriptor created on Core is modified as per SEC block
   endianness before the job is submitted.
2. The read/write of physical addresses to Job Rings will
   be depend on endianness of SEC block as 32 bit low and
   high part of the 64 bit address will vary.
3. The 32 bit low and high part of the 64 bit address in
   descriptor will vary depending on endianness of SEC.
Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Data types and I/O functions have been defined for
64 bit physical addresses in arm.
Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

For the Chain of Trust, the esbc_validate command supports
32 bit fields for location of the image. In the header structure
definition, these were declared as pointers which made them
64 bit on a 64 bit core.
Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

As QSPI/DSPI and IFC are pin multiplexed, IFC is disabled
in SD boot for QSPI. This patch will add fdt support for
this rule.
Signed-off-by: NAlison Wang <alison.wang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

As QSPI and IFC are pin-multiplexed on LS1021A, only IFC is supported in
SD boot now. For the customer's demand, QSPI needs to be supported in SD
boot too.

This patch adds QSPI or IFC support in SD boot according to the
corresponding defconfig. For detail, ls1021atwr_sdcard_ifc_defconfig is
used to support IFC in SD boot and ls1021atwr_sdcard_qspi_defconfig is
used to support QSPI in SD boot.
Signed-off-by: NAlison Wang <alison.wang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

The address of uboot changed, so change qe ucode
Signed-off-by: NZhao Qiang <B45475@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Pointer 'reg' returned from call to function 'fdt_getprop' may be
NULL, will be passed to function and may be dereferenced there by
passing argument 1 to function 'of_read_number'. So check pointer
'reg' first.
Signed-off-by: NAlison Wang <alison.wang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Currently, using fdt_fixup_stdout() on a device tree that is missing
the relevant alias results in this:

WARNING: could not set linux,stdout-path FDT_ERR_NOTFOUND.
ERROR: /chosen node create failed
 - must RESET the board to recover.

FDT creation failed! hanging...### ERROR ### Please RESET the board ###

There is no reason for this to be a fatal error rather than a warning,
and removing this allows for a smooth transition on a platform where
the device tree currently lacks the correct aliases but will have them
in the future.
Signed-off-by: NScott Wood <scottwood@freescale.com>
Cc: Kumar Gala <galak@kernel.crashing.org>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NYork Sun <yorksun@freescale.com>

This will allow OF-based earlycon to be used once the appropriate
aliases are added to the device tree and kernel support is fixed.
Signed-off-by: NScott Wood <scottwood@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

get_clocks() should not be limited by ESDHC.
Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>

We have finished Generic Board conversion for ARM and PowerPC, i.e.
all the boards have been converted except OpenRISC, SuperH, SPARC,
which have not supported Generic Board framework yet.

Select SYS_GENERIC_BOARD in arch/Kconfig and delete all the macro
defines in include/configs/*.h.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This reverts commit 321f86e1.

The original bug has been fixed.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Tested-on: Zedboard and ZC706 board
Tested-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Tested-on: zc702
Tested-by: NMichal Simek <michal.simek@xilinx.com>

We should not init the console this early since it precludes using driver
model for the UART, since it is not set up at the start of board_init_f().
See the README for more information. The debug UART does not have this
restriction. If we want to do early init with the console on it can be done
in spl_board_init().

Move the preloader_console_init() call from board_init_f() to board_init_r().
Signed-off-by: NSimon Glass <sjg@chromium.org>
Tested-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: NMichal Simek <michal.simek@xilinx.com>

This C function should be used to do the early memory layout and init. This
is beyond my powers, so just add a TODO for the maintainer.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Acked-by: NMichal Simek <michal.simek@xilinx.com>

There is quite a bit of assembler code that can be removed if we use the
generic global_data setup. Less arch-specific code makes it easier to add
new features and maintain the start-up code.

Drop the unneeded code and adjust the hooks in board_f.c to cope.
Signed-off-by: NSimon Glass <sjg@chromium.org>

There is quite a bit of assembler code that can be removed if we use the
generic global_data setup. Less arch-specific code makes it easier to add
new features and maintain the start-up code.

Drop the unneeded code and adjust the hooks in board_f.c to cope.

Tested on LS2085ARDB and LS2085AQDS (armv8 SoC).
Tested-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NSimon Glass <sjg@chromium.org>

Change the #ifdef so that the early malloc() area is not set up in SPL if
CONFIG_SYS_SPL_MALLOC_START is defined. In that case it would never actually
be used, and just chews up stack space.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Tested-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Unfortunately memset() is not always available, so provide a substitute when
needed.
Signed-off-by: NSimon Glass <sjg@chromium.org>