- 14 10月, 2011 7 次提交
-
-
由 Timur Tabi 提交于
The EC1_EXT, EC2_EXT, and EC3 bits in the RCW don't officially exist on the P3060 and should always be set to zero. Signed-off-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 chenhui zhao 提交于
Signed-off-by: NZhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 chenhui zhao 提交于
- Rework tlb and law tables. - PCI2 is not available on MPC8548CDS, so remove it. - Move the memory map to the board config file. - Rewrite the board info according to the manual. - Remove unnecessary macros and redefine some macros to align with other boards. - Fix some typos. Signed-off-by: NZhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Haiying Wang 提交于
P3041 has 10 qman portals, we need to configure all of them: * As there are only 4 physical cores sdest can only be 0 to 3 * We assign dqrr & frame data LIODNs for all portals so if they are utilized the proper mapping tables can be setup uniquely (PAMU stashing) * We set Portal 6-10 to LIODN offsets 1-5 as the global LIODN assignments are tuned around an assumption of at most 5 partitions. Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Haiying Wang 提交于
P2041 has 10 qman portals, we need to configure all of them: * As there are only 4 physical cores sdest can only be 0 to 3 * We assign dqrr & frame data LIODNs for all portals so if they are utilized the proper mapping tables can be setup uniquely (PAMU stashing) * We set Portal 6-10 to LIODN offsets 1-5 as the global LIODN assignments are tuned around an assumption of at most 5 partitions. Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Haiying Wang 提交于
P5020 has 10 qman portals, we need to configure all of them: * As there are only 2 physical cores sdest can only be 0 or 1 * We assign dqrr & frame data LIODNs for all portals so if they are utilized the proper mapping tables can be setup uniquely (PAMU stashing) * We set Portal 6-10 to LIODN offsets 1-5 as the global LIODN assignments are tuned around an assumption of at most 5 partitions. Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Kuldip Giroh 提交于
Signed-off-by: NKuldip Giroh <kuldip.giroh@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
- 13 10月, 2011 5 次提交
-
-
git://git.denx.de/u-boot-mips由 Wolfgang Denk 提交于
* 'master' of git://git.denx.de/u-boot-mips: MIPS: Jz4740: Add qi_lb60 board support MIPS: Jz4740: Add NAND driver MIPS: Ingenic XBurst Jz4740 processor support
-
git://git.denx.de/u-boot-ppc4xx由 Wolfgang Denk 提交于
* 'master' of git://git.denx.de/u-boot-ppc4xx: ppc4xx: Change DDR2 CL from 4 to 5 for intip ppc4xx: Improve lm63 pwm on dlvision-10g ppc4xx: Do not stop booting on any keypress on intip
-
git://git.denx.de/u-boot-ubi由 Wolfgang Denk 提交于
* 'master' of git://git.denx.de/u-boot-ubi: UBI: init eba tables before wl when attaching a device ubifs bad superblock bug
-
git://git.denx.de/u-boot-nand-flash由 Wolfgang Denk 提交于
* 'master' of git://git.denx.de/u-boot-nand-flash: NAND: davinci: choose correct 1-bit h/w ECC reg
-
git://git.denx.de/u-boot-microblaze由 Wolfgang Denk 提交于
* 'master' of git://git.denx.de/u-boot-microblaze: microblaze: Copy bootfile from variables microblaze: Fix unaligned.h for endians microblaze: Initialize jumptable and console microblaze: Support flashes on lower addresses microblaze: Call common console_init_f initialization function
-
- 12 10月, 2011 7 次提交
-
-
由 Xiangfu Liu 提交于
Add support for the qi_lb60 (a.k.a QI Ben NanoNote) clamshell device from Qi hardware: http://en.qi-hardware.com/wiki/Ben_NanoNote http://en.qi-hardware.com/wiki/Main_Page http://en.wikipedia.org/wiki/Qi_hardware This Jz4740-based clamshell device does not use NOR flash to boot. The initial bring-up assumes that U-Boot is directly loaded into SDRAM using USB boot tool, and starts from 0x80100000. About USB boot tool ------------------- Jz4740 is one of the XBurst processors with USB boot functionality supported. The CPU can boot from a small ROM in the LSI, initialize CPU and USB module, then wait for USB commands from the USB host. We can send 8 KB binary data to the CPU cache using USB boot tool. USB boot tool is available to the public at Ingenic website. Also there is an alternative Debian package named xburst-tools. Signed-off-by: NXiangfu Liu <xiangfu@openmobilefree.net> Acked-by: NDaniel <zpxu@ingenic.cn> Signed-off-by: NShinya Kuribayashi <skuribay@pobox.com>
-
由 Xiangfu Liu 提交于
Jz4740 NAND flash controller can support: * MLC NAND as well as SLC NAND * all 8-bit/16-bit NAND flash devices * HAMMING and RS hardware ECC * automatic boot up from NAND flash devices nand_ecclayout is set up for 2GiB NAND chip mounted in Qi LB60. We'll bring up boot-from-NAND support in nand_spl/ in the future. Signed-off-by: NXiangfu Liu <xiangfu@openmobilefree.net> Acked-by: NDaniel <zpxu@ingenic.cn> Signed-off-by: NShinya Kuribayashi <skuribay@pobox.com>
-
由 Dirk Eibach 提交于
Some intip boards don't seem to run stable with CL4, datasheets suggest that CL5 is the safe value. Signed-off-by: NDirk Eibach <eibach@gdsys.de> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Dirk Eibach 提交于
Fan PWM lookuptable was modified to start at 46 degrees celsius instead of 40 degrees celsius. Signed-off-by: NDirk Eibach <eibach@gdsys.de> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Dirk Eibach 提交于
Use CONFIG_AUTOBOOT_KEYED on intip so that booting can only be stopped with well defined keypresses. Signed-off-by: NDirk Eibach <eibach@gdsys.de> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Holger Brunck 提交于
This fixes that u-boot gets stuck when a bitflip was detected during "ubi part <ubi_device>". If a bitflip was detected UBI tries to copy the PEB to a different place. This needs that the eba table are initialized, but this was done after the wear levelling worker detects the bitflip. So changes the initialisation of these two tasks in u-boot. This is a u-boot specific patch and not needed in the linux layer, because due to commit 1b1f9a9d UBI: Ensure that "background thread" operations are really executed we schedule these tasks in place and not as in linux after the inital task which schedule this new task is finished. Signed-off-by: NHolger Brunck <holger.brunck@keymile.com> cc: Stefan Roese <sr@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
-
由 Lars Poeschel 提交于
This patch fixes an issue when ubifs reads a bad superblock. Later it tries to free memory, that was not allocated, which freezes u-boot. This is fixed by looking for a non null pointer before free. The message I got before u-boot freezes: UBI: max/mean erase counter: 53/32 UBIFS: mounted UBI device 0, volume 1, name "rootfs" UBIFS: mounted read-only UBIFS: file system size: 49140 bytes (50319360 KiB, 0 MiB, 49140 LEBs) UBIFS: journal size: 49 bytes (6838272 KiB, 0 MiB, 6678 LEBs) UBIFS: media format: w4/r0 (latest is w4/r0) UBIFS: default compressor: LZO UBIFS: reserved for root: 0 bytes (0 KiB) UBIFS error (pid 0): ubifs_read_node: bad node type (255 but expected 9) UBIFS error (pid 0): ubifs_read_node: bad node at LEB 330:13104 UBIFS error (pid 0): ubifs_iget: failed to read inode 1, error -22 Error reading superblock on volume 'ubi:rootfs'! Signed-off-by: NLars Poeschel <larsi@wh2.tu-dresden.de> Cc: Kyungmin Park <kmpark@infradead.org> Signed-off-by: NStefan Roese <sr@denx.de>
-
- 11 10月, 2011 1 次提交
-
-
由 Laurence Withers 提交于
In nand_davinci_readecc(), select the correct NANDF<n>ECC register based on CONFIG_SYS_NAND_CS rather than hardcoding the choice of NANDF1ECC. This allows 1-bit hardware ECC to work with chip select other than CS2. Note this now matches the usage in nand_davinci_enable_hwecc(), which already had the correct handling, and allows refactoring to a single function encapsulating the register read. Without this fix, writing NAND pages to a chip not wired to CS2 would result in in the ECC calculation always returning FFFFFF for each 512-byte segment, and reading back a correctly written page (one with ECC intact) would always fail. With this fix, the ECC is written and verified correctly. Signed-off-by: NLaurence Withers <lwithers@guralp.com> Signed-off-by: NScott Wood <scottwood@freescale.com>
-
- 10 10月, 2011 20 次提交
-
-
由 Xiangfu Liu 提交于
Jz4740 is a multimedia application processor targeting for mobile devices like e-Dictionary, eBook, portable media player (PMP) and GPS navigator. Jz4740 is powered by Ingenic 360 MHz XBurst CPU core (JzRISC), in which RISC/SIMD/DSP hybrid instruction set architecture provides high integration, high performance and low power consumption. JzRISC incorporated in Jz4740 is the advanced and power-efficient 32-bit RISC core, compatible with MIPS32, with 16K I-Cache and 16K D-Cache, and can operate at speeds up to 400 MHz. On-chip modules such as LCD controller, embedded audio codec, multi- channel SAR-ADC, AC97/I2S controller and camera I/F offer a rich suite of peripherals for multimedia application. NAND controller (SLC/MLC), USB (host 1.1 and device 2.0), UART, I2C, SPI, etc. are also available. For more info about Ingenic XBurst Jz4740: http://en.ingenic.cn/eng/ http://www.linux-mips.org/wiki/Ingenic This patch introduces XBurst CPU support in U-Boot. It's compatible with MIPS32, but requires a bit different cache maintenance, timer routines, and boot mechanism using USB boot tool, so XBurst support can go into a separate new home, cpu/xburst/. Signed-off-by: NXiangfu Liu <xiangfu@openmobilefree.net> Acked-by: NDaniel <zpxu@ingenic.cn> Signed-off-by: NShinya Kuribayashi <skuribay@pobox.com>
-
由 Michal Simek 提交于
Setup bootfile. Signed-off-by: NMichal Simek <monstr@monstr.eu>
-
由 Michal Simek 提交于
Also support little endian MB. Signed-off-by: NMichal Simek <monstr@monstr.eu> Acked-by: NMike Frysinger <vapier@gentoo.org>
-
由 Michal Simek 提交于
This changes were done to get support for netconsole. Signed-off-by: NMichal Simek <monstr@monstr.eu>
-
由 Michal Simek 提交于
Signed-off-by: NMichal Simek <monstr@monstr.eu>
-
由 Michal Simek 提交于
Calling console_init_f enables CTRL+C usage. Signed-off-by: NMichal Simek <monstr@monstr.eu>
-
由 Xie Xiaobo 提交于
MPC8536DS offer booting from SDcard or SPI flash. This patch defined that u-boot can save the environment variables on SDcard or SPI flash when booting from the related device. The Env parameter region and linux kernel region have overlap in SPI-Flash, So change the Env param saving address. Signed-off-by: NXie Xiaobo <r63061@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Fanzc 提交于
Add EHCI controller and USB command definition. Signed-off-by: NXie Xiaobo <r63061@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Tang Yuantian 提交于
If CONFIG_LBA48 is not defined, the element lba48 of struct sata_dev_desc is not avaible, and can't be used. Signed-off-by: NTang Yuantian <b29983@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Xie Xiaobo 提交于
MPC8536 Rev 1.0 silicon have NMG_eSDHC118 erratum, so that the SDHC write protected pin polarity does not follow the SD card standard in MPC8536 Rev 1.0 silicon. The MPC8536DS board invert the SDHC_WP pin as a workaround. However, this silicon erratum has been fixed in Rev 1.1, So need invert the SDHC_WP polarity again when use the MPC8536 Rev1.1 and greater on MPC8536DS board. Signed-off-by: NXie Xiaobo <r63061@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Xie Xiaobo 提交于
1. The SD_DATA[4:7] signals are shared with the SPI chip selects on 8536DS, so don't set MPC85xx_PMUXCR_SD_DATA that config eSDHC data bus-width to 4-bit and enable SPI signals. 2. Add eSPI controller and SPI-FLASH definition. Signed-off-by: NXie Xiaobo <r63061@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 chenhui zhao 提交于
- Increase the size of malloc space. - Enable e1000 network card. - Show pci devices on startup. - Change the location of env address. - Use hwconfig to turn off ECC by default. [Kumar Gala] Fixed white space formating for CONFIG_EXTRA_ENV_SETTINGS Signed-off-by: NZhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Becky Bruce 提交于
We really shouldn't be overwriting bat registers with translation enabled, especially when we're executing code using one of them for translating the current instruction stream. Instead, disable address translation while doing the final BAT setup. In order to do this, setup_bats has to move back to asm code, because we require translation to be enabled to have a stack for C code. The yucky thing about that is that the assembler doesn't like ULL so we have to switch to using HIGH/LOW pairs for physical addresses that are > 32 bits in length. Signed-off-by: NBecky Bruce <beckyb@kernel.crashing.org> Acked-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Becky Bruce 提交于
There were duplicate (and conflicting) defines for the BATs used to cover SRIO. Drop the bogus set. Signed-off-by: NBecky Bruce <beckyb@kernel.crashing.org> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Timur Tabi 提交于
Function dtsec_configure_serdes() needs to know where the TBI PHY registers are in order to configure SGMII for proper SerDes operation. During SGMII initialzation, fm_eth_init_mac() passing NULL for 'phyregs' when it called init_dtsec(), because it was believed that phyregs was not used. In fact, it is used by dtsec_configure_serdes() to configure the TBI PHY registers. We also need to define the PHY registers in struct fm_mdio. Signed-off-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 York Sun 提交于
It is not necessary to keep multiple entries for the same setting in DDR speed tables. Merge them for smaller tables. Also restructure the tables for smaller size. Cleanup some typedefs. Enforce strict checking for speed table. If DIMM is running at higher than known speed, try to use the highest speed setting. If rank is unknown, it has to panic. Removed ODT overriding for P2020DS as it is not necessary. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Andy Fleming 提交于
The Teranetics PHY does not properly report the link state for fiber connections. The new PHY code actually checked the link, and so the FM driver would refuse to talk over a linkless PHY. But the link may actually be up, so now we always report it as up for fiber connections on the tn2020. Signed-off-by: NAndy Fleming <afleming@freescale.com>
-
由 Timur Tabi 提交于
The macro CONFIG_ENABLE_36BIT_PHYS is used to indicate that the given SOC is capable of 36-bit physical addresses, even if such large addresses are not used. On two boards, this macro was enabled only when building a 36-bit image. Signed-off-by: NTimur Tabi <timur@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 York Sun 提交于
Interactive DDR debugging provides a user interface to view and modify SPD, DIMM parameters, board options and DDR controller registers before DDR is initialized. With this feature, developers can fine-tune DDR for board bringup and other debugging without frequently having to reprogram the flash. To enable this feature, define CONFIG_FSL_DDR_INTERACTIVE in board header file and set an environment variable to activate it. Syntax: setenv ddr_interactive on After reset, U-boot prompts before initializing DDR controllers FSL DDR> The available commands are print print SPD and intermediate computed data reset reboot machine recompute reload SPD and options to default and recompute regs edit modify spd, parameter, or option compute recompute registers from current next_step to end next_step shows current next_step help this message go program the memory controller and continue with u-boot The first command should be "compute", which reads data from DIMM SPDs and board options, performs the calculation then stops before setting DDR controller. A user can use "print" and "edit" commands to view and modify anything. "Go" picks up from current step with any modification and compltes the calculation then enables the DDR controller to continue u-boot. "Recompute" does it over from fresh reading. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
-
由 Wolfgang Denk 提交于
Fix: usb_ohci.c: In function 'dl_transfer_length': usb_ohci.c:768:8: warning: variable 'tdINFO' set but not used [-Wunused-but-set-variable] Signed-off-by: NWolfgang Denk <wd@denx.de> Cc: Remy Bohmer <linux@bohmer.net>
-