A malloc() followed by memset() can be simply replaced by calloc().
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

If failed the add_host(), it is reasonable that return value of
add_sdhci().
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Signed-off-by: NVipin Kumar <vipin.kumar@st.com>
Acked-by: NStefan Roese <sr@denx.de>
Acked-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Without this additional delay, some eMMC don't negotiate properly bus width
Tested on:
 - Toshiba THGBM2G8D8FBAIB
 - Toshiba THGBM4G4D1HBAR
 - Micron MTFC4GMVEA (the one giving the problem)
 - Hynix H26M64002BNR
 - SanDisk SDIN5E1-32G
Signed-off-by: NDavide Bonfanti <davide.bonfanti@bticino.it>
Acked-by: NTom Rini <trini@ti.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Most of time that MMC driver spends on initializing a device is polling
OCR (operation conditions register).  To decouple this polling loop,
device init is split into two parts: The first part fires the OCR query
command, and the second part polls the result.  So the caller is now no
longer bound to the OCR-polling delay; he may fire the query, go
somewhere and then come back later for the result.

To use this, call mmc_set_preinit() on any device which needs this.

This can save significant amounts of time on boot (e.g. 200ms) by
hiding the MMC init time behind other init.
Signed-off-by: NChe-Liang Chiou <clchiou@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>
Acked-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

We can use a common global method for calculating minimum of
3 numbers. Put the same in 'common header' and let 'ehci'
use it.
Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com>
Acked-by: NTom Rini <trini@ti.com>

Fix the Port status bit constants and Port feature number
constants as a part of USB 2.0 and USB 3.0 Hub class.
Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com>

Untill now we power-cycle (aka: disable power on a port
and re-enabling again) one port at a time.
Delay of 20ms for Port-power to change multiplies with
number of ports in this case.
So better we parallelize this process:
disable power on all ports, wait for port-power to stabilize
and then re-enable the power subsequently.
Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com>

The at91sam9g10 need to configure HCK0 to make OHCI work
Signed-off-by: NBo Shen <voice.shen@atmel.com>

This adds usb framework support for super-speed usb, which will
further facilitate to add stack support for xHCI.
Signed-off-by: NVikas C Sajjan <vikas.sajjan@samsung.com>
Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com>

Patch b6d7852c increases timeout for enumeration, taking
worst case to be 10 sec.
get_timer() api returns timestamp in milliseconds, which is
what we are checking in the do-while() loop in usb_hub_configure()
(get_timer(start) < CONFIG_SYS_HZ * 10).
This should give us a required check for 10 seconds, and thereby
we don't need to add additional mdelay of 100 microseconds in
each cycle.
Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com>
Reviewed-by: NVipin Kumar <vipin.kumar@st.com>

Fetch the device class into usb device's dwcriptors,
so that the host controller's driver can use this info
to differentiate between HUB and DEVICE.
Signed-off-by: NAmar <amarendra.xt@samsung.com>

XHCI ports are powered on after a H/W reset, however
EHCI ports are not. So disabling and re-enabling power
on all ports invariably.
Signed-off-by: NAmar <amarendra.xt@samsung.com>
Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com>

Some cleanup in usb framework, nothing much on feature side.
Signed-off-by: NVikas C Sajjan <vikas.sajjan@samsung.com>
Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com>

USB_PRINTF, USB_HUB_PRINTF, USB_STOR_PRINTF, USB_KBD_PRINTF
are nothing but conditional debug prints, depending on DEBUG.
So better remove them and use debug() simply.
Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com>

This patch adds a new 'usb test' command, that will set a port to a USB
2.0 test mode (see USB 2.0 spec 7.1.20). It supports all five test modes
on both downstream hub ports and ordinary device's upstream ports. In
addition, it supports EHCI root hub ports.
Signed-off-by: NJulius Werner <jwerner@chromium.org>

Add ehci_get_port_speed() and ehci_set_usbmode() weak functions
for platform driver to support new chip.
Signed-off-by: NJim Lin <jilin@nvidia.com>

With the u-boot-with-spl.bin rule calling $(OBJCOPY) with
CONFIG_SPL_PAD_TO, and CONFIG_SPL_PAD_TO defaulting to
CONFIG_SPL_MAX_SIZE we cannot use math here, so set it to 4096 rather
than 4 * 1024.
Signed-off-by: NTom Rini <trini@ti.com>

The Hydra and Superhydra (P3041DS, P5020DS, and P5040DS) boards have a
second USB port that can be configured in either host, peripheral (aka
device), or OTG (on-the-go) mode.  When configured in host mode, if
the port is connected to another USB host, damage to the board can
occur.

To avoid this, we change the default setting to peripheral mode.  Ideally,
we'd set it to OTG mode, but currently there is no OTG support for
these boards.

Setting the hwconfig variable will also update the device tree, and so
Linux will configure the port for peripheral mode as well.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: NTimur Tabi <timur@tabi.org>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

When P1021RDB-PC reboot system, the board will hung at uboot DDR
configuration. For P1021RDB-PC DDR reset pin is multiplex with
QE, so uboot will reserve this pin for QE and skip DDR reset.
Other platforms without QE will do this reset. This patch adds
a slight code to reset DDR chip by QE CE_PB8 pin for NAND and
NOR FLASH boot. For booting from SPI FALSH and SD card, it
seems possible to use the rom on chip to write to the GPIO
pins before configuring the DDR.
Signed-off-by: NXu Jiucheng <B37781@freescale.com>
Signed-off-by: NXie Xiaobo <X.Xie@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Extending LIODN offset range from 1-5 to 1-10
While using a qman portal with a higher index the LIODN offset
is incorrectly set, thus extending the range of offsets covers
all 10 qman portals
Signed-off-by: NCristian Sovaiala <cristian.sovaiala@freescale.com>
Acked-by: NHaiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Erratum DDR_A003 applies to P5020, P3041, P4080, P3060, P2041, P5040.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Change flexcan compatible string from "fsl,flexcan-v1.0"
to "fsl,p1010-flexcan" to match the device tree.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Only some chips have four SerDes banks, so don't define lanes for a bank
that doesn't exist.
Signed-off-by: NTimur Tabi <timur@tabi.org>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Resolve P1020 second USB controller multiplexing with eLBC
         - mandatory to mention USB2 in hwconfig string to select it
           over eLBC, otherwise USB2 node is removed
         - works only for SPI and SD boot
Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Signed-off-by: NZhicheng Fan <B32736@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

There could be scenarios where the user would like to manually(via JTAG)
configure the DDR/L2SRAM and load the bootloader binary onto DDR/L2SRAM.
This document explains thse usecases and the detailed explanation of what needs
to be done to use it.

Most of the code from CONFIG_SYS_RAMBOOT will be used except for small changes
of CCSRBAR etc.

The changes are not very large, but it is good to document them so that user
can get it working at once.
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

As per Errata list of BSC9131 and BSC9132, IFC Errata A003399 is no more
valid. So donot compile its workaround.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

cpu.c:288:2:
warning: implicit declaration of function 'reset_85xx_watchdog'
[-Wimplicit-function-declaration]
Signed-off-by: NHorst Kronstorfer <hkronsto@frequentis.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

On P204x/P304x/P50x0 Rev1.0, USB transmit will result in false internal
multi-bit ECC errors, which has impact on performance, so software should
disable all ECC reporting from USB1 and USB2.

In formal release document, the errata number should be USB14 instead of USB138.
Signed-off-by: Nxulei <Lei.Xu@freescale.com>
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Signed-off-by: Nxulei <B33228@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Add the tlb entries based on the configuration of the SRIO interfaces.
Every SRIO interface has 256M space:

	#define CONFIG_SYS_SRIO1_MEM_VIRT   0xa0000000
	#define CONFIG_SYS_SRIO1_MEM_PHYS   0xc20000000ull

	#define CONFIG_SYS_SRIO2_MEM_VIRT   0xb0000000
	#define CONFIG_SYS_SRIO2_MEM_PHYS   0xc30000000ull
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Some legacy RGMII phys don't have in band signaling for the
speed information. so set the RGMII MAC mode according to
the speed got from PHY.
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Reported-by: NJohn Traill <john.traill@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

For T4/B4, the clockgen node compatible string is updated to version 2.
Add clock-frequency setting for this new version.
Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Per the latest errata updated, B4860/B4420 Rev 1.0 has also
errata A-005871, so adding define A-005871 for B4 SoCs.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

B4420/B4860 PCIE can not work because of the wrong definition of
the PCIE register offset in the file:
	arch/powerpc/include/asm/immap_85xx.h

Add the judgement of B4420/B4860 to make the register offset to:
	#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET         0x200000
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Add defines needed to access NAND, remove second flash bank that is
actually connected to NAND.

Add nand booting support for P1022DS with hardcoded DDR config using
SPL framework from 2011
Signed-off-by: NMatthew McClintock <msm@freescale.com>
Signed-off-by: NJerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: NJiang Yutang <b14898@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Set the device tree property associated with the mpic source
frequency. The frequency is used for mpic timer.
Signed-off-by: NWang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

The 'fsl,pme-rev1' and 'fsl-pme-rev2' properties have been added to the
pme portal node. This is required for software to determine which version
of PME hardware is present and take appropriate actions.
These properties are a direct reflection of the corresponding ccsr pme
register value.

Also removed unnecessary static global variables.
Signed-off-by: NJeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>