T4240 PCIe IP is version 3.0 and has some update comparing previous
QorIQ products.

1.  Move Freescale specific register define
to
arch/powerpc/include/asm/fsl_pci.h
and update the register offset define for T4240.

2. add the status/control register define
use status/control register to judge the link status

3. The original code uses 'Programming Interface' field to judge if PCIE is
EP or RC mode, however, T4240 does not support this functionality.
According to PCIE specification, 'Header Type' offset 0x0e is used to
indicate header type, so for PCIE controller, the patch changes code to
use 'Header Type' field to identify if the PCIE is RC or EP mode.

This patch fixes  the PCIe card link up issue on T4240QDS.
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>

Signed-off-by: NWolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: NTom Rini <trini@ti.com>

Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable
the master module of Boot from SRIO and PCIE on a platform. But this
is not a silicon feature, it's just a specific booting mode based on
the SRIO and PCIE interfaces. So it's inappropriate to put the macro
into the file arch/powerpc/include/asm/config_mpc85xx.h.

Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to
"CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from
arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros
in configuration header file of each board which can support the
master module of Boot from SRIO and PCIE.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Due to SerDes configuration error, if we set the PCI-e controller link width
as x8 in RCW and add a narrower width(such as x4, x2 or x1) PCI-e device to
PCI-e slot, it fails to train down to the PCI-e device's link width. According
to p4080ds errata PCIe-A003, we reset the PCI-e controller link width to x4 in
u-boot. Then it can train down to x2 or x1 width to make the PCI-e link between
RC and EP.
Signed-off-by: NYuanquan Chen <B41889@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Currently, the SRIO and PCIE boot master module will be compiled into the
u-boot image if the macro "CONFIG_FSL_CORENET" has been defined. And this
macro has been included by all the corenet architecture platform boards.
But in fact, it's uncertain whether all corenet platform boards support
this feature.

So it may be better to get rid of the macro "CONFIG_FSL_CORENET", and add
a special macro for every board which can support the feature. This
special macro will be defined in the header file
"arch/powerpc/include/asm/config_mpc85xx.h". It will decide if the SRIO
and PCIE boot master module should be compiled into the board u-boot image.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Add support for Freescale T4240 SoC. Feature of T4240 are
(incomplete list):

12 dual-threaded e6500 cores built on Power Architecture® technology
  Arranged as clusters of four cores sharing a 2 MB L2 cache.
  Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture
    v2.06-compliant)
  Three levels of instruction: user, supervisor, and hypervisor
1.5 MB CoreNet Platform Cache (CPC)
Hierarchical interconnect fabric
  CoreNet fabric supporting coherent and non-coherent transactions with
    prioritization and bandwidth allocation amongst CoreNet end-points
  1.6 Tbps coherent read bandwidth
  Queue Manager (QMan) fabric supporting packet-level queue management and
    quality of service scheduling
Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
    support
  Memory prefetch engine (PMan)
Data Path Acceleration Architecture (DPAA) incorporating acceleration for
    the following functions:
  Packet parsing, classification, and distribution (Frame Manager 1.1)
  Queue management for scheduling, packet sequencing, and congestion
    management (Queue Manager 1.1)
  Hardware buffer management for buffer allocation and de-allocation
    (BMan 1.1)
  Cryptography acceleration (SEC 5.0) at up to 40 Gbps
  RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps
  Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps
  DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0)
32 SerDes lanes at up to 10.3125 GHz
Ethernet interfaces
  Up to four 10 Gbps Ethernet MACs
  Up to sixteen 1 Gbps Ethernet MACs
  Maximum configuration of 4 x 10 GE + 8 x 1 GE
High-speed peripheral interfaces
  Four PCI Express 2.0/3.0 controllers
  Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with
    Type 11 messaging and Type 9 data streaming support
  Interlaken look-aside interface for serial TCAM connection
Additional peripheral interfaces
  Two serial ATA (SATA 2.0) controllers
  Two high-speed USB 2.0 controllers with integrated PHY
  Enhanced secure digital host controller (SD/MMC/eMMC)
  Enhanced serial peripheral interface (eSPI)
  Four I2C controllers
  Four 2-pin or two 4-pin UARTs
  Integrated Flash controller supporting NAND and NOR flash
Two eight-channel DMA engines
Support for hardware virtualization and partitioning enforcement
QorIQ Platform's Trust Architecture 1.1
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Signed-off-by: NAndy Fleming <afleming@freescale.com>
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Fix compiling error in case CONFIG_SYS_PCIE2_MEM_VIRT or CONFIG_SYS_PCIE3_MEM_VIRT
not defined.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

The original code uses 'Programming Interface' field to judge if PCIE is
EP or RC mode, however, T4240 does not support this functionality.
According to PCIE specification, 'Header Type' offset 0x0e is used to
indicate header type, so for PCIE controller, the patch changes code to
use 'Header Type' field to identify if the PCIE is EP or RC mode.
Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

For the powerpc processors with PCIE interface, boot location can be
configured from one PCIE interface by RCW. The processor booting from PCIE
can do without flash for u-boot image. The image can be fetched from another
processor's memory space by PCIE link connected between them.

The processor booting from PCIE is slave, the processor booting from normal
flash memory space is master, and it can help slave to boot from master's
memory space.

When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.

Environment and requirement:

master:
    1. NOR flash for its own u-boot image, ucode and ENV space.
    2. Slave's u-boot image is in master NOR flash.
    3. Normally boot from local NOR flash.
    4. Configure PCIE system if needed.
slave:
    1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
    2. Boot location should be set to one PCIE interface by RCW.
    3. RCW should configure the SerDes, PCIE interfaces correctly.
	4. Must set all the cores in holdoff by RCW.
	5. Must be powered on before master's boot.

For the master module, need to finish these processes:
    1. Initialize the PCIE port and address space.
    2. Set inbound PCIE windows covered slave's u-boot image stored in
       master's NOR flash.
	3. Set outbound windows in order to configure slave's registers
	   for the core's releasing.
    4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2"
	   or "PCIE3" using the following command:

			setenv bootmaster PCIE1
			saveenv
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

The FSL PCI driver uses local prototypes for
pciauto_[pre|post]scan_setup_bridge(), this does not seem right,
so move them to the <pci.h> file.

Fixed a small extern declaration too, this is harmless but distracts
the view since all other prototypes are explicitly external.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Fixing build regressions for the Integrator I get find that a few
boards try to work around the missing declaration of
pciauto_config_init() by declaring it in the local scope. This
does not make sense when the sibling functions are in <pci.h>
so move the function to the header, ridding the build error
in the Integrator and getting rid of the local declarations
here and there.
Reported-by: NWolfgang Denk <wd@denx.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

fsl_pci_init.c: In function 'fsl_pci_init':
fsl_pci_init.c:308: warning: format '%08x' expects type 'unsigned int', but
argument 6 has type 'long unsigned int'
fsl_pci_init.c:347: warning: format '%x' expects type 'unsigned int', but
argument 2 has type 'volatile u32 *'

fsl_pci_init.c: In function 'fsl_pci_init':
fsl_pci_init.c:308: warning: format '%016llx' expects type 'long long unsigned
int', but argument 4 has type 'pci_addr_t'
fsl_pci_init.c:308: warning: format '%016llx' expects type 'long long unsigned
int', but argument 5 has type 'pci_size_t'
fsl_pci_init.c:308: warning: format '%08x' expects type 'unsigned int', but
argument 6 has type 'long unsigned int'
Signed-off-by: NMarek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>

Recieve/Receive
recieve/receive
Interupt/Interrupt
interupt/interrupt
Addres/Address
addres/address
Signed-off-by: NMike Williams <mike@mikebwilliams.com>

FSL PCIe controller v2.1:
	- New MSI inbound window
	- Same Inbound windows address as PCIe controller v1.x

Added new pit_t member(pmit) to struct ccsr_pci for MSI inbound window

FSL PCIe controller v2.2 and v2.3:
	- Different addresses for PCIe inbound window 3,2,1
	- Exposed PCIe inbound window 0
	- New PCIe interrupt status register

Added new Interrupt Status register to struct ccsr_pci & updated pit_t array
size to reflect the 4 inbound windows.

To maintain backward compatiblilty, on V2.2 or greater controllers we
start with inbound window 1 and leave inbound 0 with its default value
(which maps to CCSRBAR).
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require
that we initialize the SERDES registers if the lanes are configured for
PCIe.  Additionally these devices PCIe controller do not support ASPM
and we have to explicitly disable it.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NWolfgang Denk <wd@denx.de>

This change does the following:
- Adds printing of negotiated link width.  This information can be
  useful when debugging PCIe issues.
- Makes it optional for boards to implement board_serdes_name().
  Previously boards that did not implement it would print unsightly
  output such as "PCIE1: Connected to <NULL>..."
- Rewords the PCIe boot output to reduce line length and to make it
  clear that the "base address XYZ" value refers to the base address of
  the internal processor PCIe registers and not a standard PCI BAR
  value.
- Changes "PCIE" output to the standard "PCIe"

Before change:
PCIE1: connected to <NULL> as Root Complex (base addr ef008000)
  01:00.0     - 10b5:8518 - Bridge device
   02:01.0    - 10b5:8518 - Bridge device
   02:02.0    - 10b5:8518 - Bridge device
   02:03.0    - 10b5:8518 - Bridge device
PCIE1: Bus 00 - 05
PCIE2: connected to <NULL> as Endpoint (base addr ef009000)
PCIE2: Bus 06 - 06

After change:
PCIe1: Root Complex of PEX8518 Switch, x4, regs @ 0xef008000
  01:00.0     - 10b5:8518 - Bridge device
   02:01.0    - 10b5:8518 - Bridge device
   02:02.0    - 10b5:8518 - Bridge device
   02:03.0    - 10b5:8518 - Bridge device
PCIe1: Bus 00 - 05
PCIe2: Endpoint of VPX Fabric A, x2, regs @ 0xef009000
PCIe2: Bus 06 - 06
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Since all the PCIe controllers are connected over SERDES on the SoCs we
can utilize is_serdes_configured() to determine if a controller is
enabled.  After which we can setup the ATMUs and LAWs for the controller
in a common fashion and allow board code to specify what the controller
is connected to for reporting reasons.

We also provide a per controller (rather than all) for some systems that
may have special requirements.

Finally, we refactor the code used by the P1022DS to utilize the new
generic code.

Based on patch by: Li Yang <leoli@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Previously we passed in a specifically named struct pci_controller to
determine if we had setup the particular PCI bus.  Now we can search for
the struct so we dont have to depend on the name or the struct being
statically allocated.

Introduced new find_hose_by_cfg_addr() to get back a pci_controller struct
back by searching for it means we can do things like dynamically allocate
them or not have to expose the static structures to all users.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Acked-by: NWolfgang Denk <wd@denx.de>

The "Scanning PCI bus X" message doesn't provide any real useful
information, so remove it.

Original output:
  PCIE1: connected as Root Complex
             Scanning PCI bus 01
          04  01  8086  1010  0200  00
          04  01  8086  1010  0200  00
          03  00  10b5  8112  0604  00
          02  01  10b5  8518  0604  00
          02  02  10b5  8518  0604  00
          08  00  1957  0040  0b20  00
          07  00  10b5  8518  0604  00
          09  00  10b5  8112  0604  00
          07  01  10b5  8518  0604  00
          07  02  10b5  8518  0604  00
          06  00  10b5  8518  0604  00
          02  03  10b5  8518  0604  00
          01  00  10b5  8518  0604  00
  PCIE1: Bus 00 - 0b
  PCIE2: connected as Root Complex
             Scanning PCI bus 0d
          0d  00  1957  0040  0b20  00
  PCIE2: Bus 0c - 0d

Updated output:
  PCIE1: connected as Root Complex
          04  01  8086  1010  0200  00
          04  01  8086  1010  0200  00
          03  00  10b5  8112  0604  00
          02  01  10b5  8518  0604  00
          02  02  10b5  8518  0604  00
          08  00  1957  0040  0b20  00
          07  00  10b5  8518  0604  00
          09  00  10b5  8112  0604  00
          07  01  10b5  8518  0604  00
          07  02  10b5  8518  0604  00
          06  00  10b5  8518  0604  00
          02  03  10b5  8518  0604  00
          01  00  10b5  8518  0604  00
  PCIE1: Bus 00 - 0b
  PCIE2: connected as Root Complex
          0d  00  1957  0040  0b20  00
  PCIE2: Bus 0c - 0d
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
CC: galak@kernel.crashing.org

Previously boards used a variety of indentations, newline styles, and
colon styles for the PCI information that is printed on bootup.  This
patch unifies the style to look like:

...
NAND:  1024 MiB
PCIE1: connected as Root Complex
           Scanning PCI bus 01
        04  01  8086  1010  0200  00
        04  01  8086  1010  0200  00
        03  00  10b5  8112  0604  00
        02  01  10b5  8518  0604  00
        02  02  10b5  8518  0604  00
        08  00  1957  0040  0b20  00
        07  00  10b5  8518  0604  00
        09  00  10b5  8112  0604  00
        07  01  10b5  8518  0604  00
        07  02  10b5  8518  0604  00
        06  00  10b5  8518  0604  00
        02  03  10b5  8518  0604  00
        01  00  10b5  8518  0604  00
PCIE1: Bus 00 - 0b
PCIE2: connected as Root Complex
           Scanning PCI bus 0d
        0d  00  1957  0040  0b20  00
PCIE2: Bus 0c - 0d
In:    serial
...
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
CC: wd@denx.de
CC: sr@denx.de
CC: galak@kernel.crashing.org

Previously fsl_pci_init_port() always assumed that a port was a PCIe
port and would incorrectly print messages for a PCI port such as the
following on bootup:
    PCI1:  32 bit, 33 MHz, sync, host, arbiter
                Scanning PCI bus 00
    PCIE1 on bus 00 - 00

This change corrects the output of fsl_pci_init_port():
    PCI1:  32 bit, 33 MHz, sync, host, arbiter
                Scanning PCI bus 00
    PCI1 on bus 00 - 00
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>

Add a new 'pci enum' command which re-enumerates the PCI buses.  This
command is enabled via the CONFIG_CMD_PCI_ENUM define and can be useful
in boards with FPGAs connected via PCI/PCIe, boards that support PCI
hot-plugging, or during PCI debug.

Also enable the 'pci enum' command for X-ES's Freescale-based boards.
Signed-off-by: NJohn Schmoller <jschmoller@xes-inc.com>
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
Acked-by: NKumar Gala <galak@kernel.crashing.org>
Acked-by: NWolfgang Denk <wd@denx.de>

Previously we used an alias the pci node to determine which node to
fixup or delete.  Now we use the new fdt_node_offset_by_compat_reg to
find the node to update.

Additionally, we replace the code in each board with a single macro call
that makes assumes uniform naming and reduces duplication in this area.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

If the PCI controller wasn't configured or enabled delete from the
device tree (include its alias).

For the case that we didn't even configure u-boot with knowledge of
the controller we can use the fact that the pci_controller pointer
is NULL to delete the node in the device tree.  We determine that
a controller was not setup (because of HW config) based on the fact
that cfg_addr wasn't setup.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

All users of is_fsl_pci_agent have been converted to fsl_is_pci_agent
that uses the standard PCI programming model to determine host vs
agent/end-point.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

commit 70ed869e broke fsl pcie end-point initialization.
Returning 0 is not correct.  The function must return the first free
bus number for the next controller.

fsl_pci_init() must still be called and a bus allocated even if the
controller is an end-point.
Signed-off-by: NEd Swarthout <Ed.Swarthout@freescale.com>
Acked-by: NVivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

This reverts commit 70ed869e.

There isn't any need to modify the API for fsl_pci_init_port to pass the
status of host/agent(end-point) status.  We can determine that
internally to fsl_pci_init_port.  Revert the patch that makes the API
change.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Originally written by Jason Jin and Mingkai Hu for mpc8536.

When QorIQ based board is configured as a PCIe agent, then unlock/enable
inbound PCI configuration cycles and init a 4K inbound memory window;
so that a PCIe host can access the PCIe agents SDRAM at address 0x0

* Supported in fsl_pci_init_port() after adding pcie_ep as a param
* Revamped copyright in drivers/pci/fsl_pci_init.c
* Mods in 85xx based board specific pci init after this change
Signed-off-by: NVivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

General code cleanup to use in/out IO accessors as well as making
the code that prints out info sane between board and generic fsl pci
code.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

General code cleanup to use in/out IO accessors as well as making
the code that prints out info sane between board and generic fsl pci
code.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

fsl_pci_init_port can be called from board specific PCI initialization
routines to setup the PCI (or PCIe) controller.  This will reduce code
redundancy in most of the 85xx/86xx FSL board ports that setup PCI.
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The old PCI ATMU setup code would just mimic the PCI regions into the
ATMU registers.  For simple memory maps in which all memory, MMIO, etc
space fit into 4G this works ok.  However there are issues with we have
>4G of memory as we know can't access all of memory and we need to
ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with
anything since we can't turn it off.

We first setup outbound windows based on what the board code setup
in the pci regions for MMIO and IO access.  Next we place PCICSRBAR
below the MMIO window.  After which we try to setup the inbound windows
to map as much of memory as possible.

On PCIe based controllers we are able to overmap the ATMU setup since
RX & TX links are separate but report the proper amount of inbound
address space to the region tracking to ensure there is no overlap.

On PCI based controllers we use as many inbound windows as available to
map as much of the memory as possible.

Additionally we changed all the CCSR register access to use proper IO
accessor functions.  Also had to add CONFIG_SYS_CCSRBAR_PHYS to some
86xx platforms that didn't have it defined.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Change the code to use the PCIe capabilities register to determine if we
are a PCIe controller or not.  Additionally cleaned up some white space
and formatting in the file.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Every platform that calls fsl_pci_init calls fsl_pci_setup_inbound_windows
before it calls fsl_pci_init.  There isn't any reason to just call it
from fsl_pci_init and simplify things a bit.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Every platform that calls fsl_pci_init calls pci_setup_indirect before
it calls fsl_pci_init.  There isn't any reason to just call it from
fsl_pci_init and simplify things a bit.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Rename the pci header for FSL HW so we can move some prototypes
in there and stop doing explicit externs
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and
can be confusing when reading the code.

Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used
for system memory mapping purposes.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add fsl_pci_config_unlock() function to enable a
PCI/PCIe interface configured in agent/endpoint mode to
respond to inbound PCI configuration cycles.
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>

fsl_pci_init.c: In function 'fsl_pci_setup_inbound_windows':
fsl_pci_init.c:122: warning: comparison is always true due to limited range of data type

The check only makes sense if we are CONFIG_PHYS_64BIT
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>