- 26 7月, 2014 19 次提交
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由 Hao Zhang 提交于
By default all DSPs are turned off, for another case option to turn off them is added in this commit. Also add command to turn off itself. Acked-by: NMurali Karicheri <m-maricheri2@ti.com> Signed-off-by: NHao Zhang <hzhang@ti.com> Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>
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由 Hao Zhang 提交于
The SoC related common functions in board.c should be placed to a common keystone.c arch file. Acked-by: NMurali Karicheri <m-maricheri2@ti.com> Signed-off-by: NHao Zhang <hzhang@ti.com> Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>
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由 Khoronzhuk, Ivan 提交于
This driver is needed in case if keystone driver is used. Currently only keystone_net driver uses it. So to avoid redundant code compilation make the keystone_nav dependent on keystone net driver. It also leads to compilation errors for boards that does't use it. Acked-by: NMurali Karicheri <m-karicheri2@ti.com> Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>
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由 Hao Zhang 提交于
Add DDR3 PHY configs updated for PG 2.0 Also add DDR3A PHY reset before init for PG2.0 SoCs. Acked-by: NMurali Karicheri <m-maricheri2@ti.com> Signed-off-by: NHao Zhang <hzhang@ti.com> Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>
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由 Khoronzhuk, Ivan 提交于
It's convinient to hold ddr3 function definitions in separate file such as ddr3.h. So move this from hardware.h to ddr3.h. Acked-by: NMurali Karicheri <m-karicheri2@ti.com> Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>
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由 Khoronzhuk, Ivan 提交于
Use common keystone2 Power Sleep controller base address instead of directly deciding which keystone2 SoC is used in psc module. Acked-by: NMurali Karicheri <m-karicheri2@ti.com> Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>
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由 Stefan Roese 提交于
Use generic board setup functions by defining CONFIG_SYS_GENERIC_BOARD. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Tom Rini <trini@ti.com>
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由 Stefan Roese 提交于
These functions have been merged into the common GPMC init code with this commit a0a37183 (ARM: omap: merge GPMC initialization code for all platform). The file is not compiled any more. So remove it as well. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Pekon Gupta <pekon@ti.com> Cc: Tom Rini <trini@ti.com> Acked-by: NPekon Gupta <pekon@ti.com>
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由 Stefan Roese 提交于
Commit a0a37183 (ARM: omap: merge GPMC initialization code for all platform) broke NAND on OMAP3 based platforms. I noticed this while testing the latest 2014.07-rc version on the TAO3530 board. NAND detection did not work with this error message: NAND: nand: error: Unable to find NAND settings in GPMC Configuration - quitting As OMAP3 configs don't set CONFIG_NAND but CONFIG_NAND_CMD. the GPMC was not initialized for NAND at all. This patch now fixes this issue. Tested on TAO3530 board. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Pekon Gupta <pekon@ti.com> Cc: Tom Rini <trini@ti.com> Acked-by: NPekon Gupta <pekon@ti.com>
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由 Andreas Bießmann 提交于
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com> Cc: Thomas Weber <thomas.weber@corscience.de>
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由 Tom Rini 提交于
As noted by clang, we have been shifting certain values out of 32bit range when setting some DDR registers. Upon further inspection these had been touching reserved fields (and having no impact). These came in from historical bring-up code and can be discarded. Similarly, we had been declaring some fields as 0 when they will be initialized that way. Tested on Beaglebone White. Reported-by: NJeroen Hofstee <jeroen@myspectrum.nl> Cc: Ash Charles <ash@gumstix.com> Signed-off-by: NTom Rini <trini@ti.com> Tested-By: NAsh Charles <ashcharles@gmail.com>
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由 Khoronzhuk, Ivan 提交于
Add script to automate NAND flash process. As for now the board has two burn scripts - burn to boot from SPI NOR flash and burn to boot from AEMIF NAND flash, rename burn_uboot script to burn_uboot_spi. Also update README to contain NAND burn U-boot process description. Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com> Acked-by: NMurali Karicheri <m-karicheri2@ti.com>
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由 Khoronzhuk, Ivan 提交于
Add support for NAND gpheader image. TI Keystone2 ROM bootloader expects 8 bytes of trailing zeroes in the nand u-boot image. So add zeros at the end of the nand gph image. Acked-by: NMurali Karicheri <m-karicheri2@ti.com> Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>
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由 Khoronzhuk, Ivan 提交于
The Keystone SoCs use the same NAND driver as Davinci. This patch adds opportunity to write Keystone U-boot image to NAND device using appropriate RBL ECC layout. This is needed only if RBL boots U-boot from NAND device and that's supposed that raw u-boot partition is used only for writing image. The main problem is that default Davinci ECC layout is different from Keystone RBL layout. To read U-boot image the RBL needs that image was written using RBL ECC layout. The BBT table is written using default Davinci layout and has to be updated using one. The BBT can be updated only while erasing chip or by forced bad block assigning, so erase function has to use native ecc layout in order to be able to write BBT correctly. So if we're writing to NAND U-boot address we use RBL layout for others we use default ECC layout. Also remove definition for CONFIG_CMD_NAND_ECCLAYOUT as there is no reasons to use ECC layout commands. It was added by mistake. Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com>
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由 Tom Rini 提交于
Add in an init function for the drivers/power framework so we can dump and read the registers via i2c. Cc: Łukasz Majewski <l.majewski@samsung.com> Signed-off-by: NTom Rini <trini@ti.com>
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由 Tom Rini 提交于
As this is a weak function that we may override, provide a prototype for it. Cc: Łukasz Majewski <l.majewski@samsung.com> Signed-off-by: NTom Rini <trini@ti.com>
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由 Mugunthan V N 提交于
Set the active_slave to 1 as slave 1 is pinned out in dra72x base board Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
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由 Mugunthan V N 提交于
Add cpsw second slave port pinmux to use it as primary ethernet port Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
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由 Mugunthan V N 提交于
Add support for using the second slave port of cpsw to be used as primary ethernet. Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
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- 05 7月, 2014 15 次提交
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由 Chin Liang See 提交于
To move the arch common function away from board folder to arch/arm/cpu/armv7/socfpga folder. Its to avoid code duplication for other non Altera dev kit which is using socfpga device. Signed-off-by: NChin Liang See <clsee@altera.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Acked-by: NDetlev Zundel <dzu@denx.de>
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由 Linus Walleij 提交于
Turn on generic board for the integrators, as per the request in the startup message. Everything just works, tested on the Integrator/AP and Integrator/CP. Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Stephen Warren 提交于
Serial port, SD card, and LCD all work. Signed-off-by: NStephen Warren <swarren@wwwdotorg.org> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Christian Riesch 提交于
Signed-off-by: NChristian Riesch <christian.riesch@omicron.at>
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由 Shaibal.Dutta 提交于
Fix following compilation error when CONFIG_ARM64 is defined Error: unknown or missing system register name at operand 2 -- `mrs x0,daifmsr daifset,#3' Signed-off-by: NShaibal.Dutta <shaibal.dutta@broadcom.com> Signed-off-by: NDarwin Rambo <drambo@broadcom.com> Reviewed-by: NDarwin Rambo <drambo@broadcom.com>
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由 Łukasz Dałek 提交于
Enable 'generic board init' for H2200 palmtop. Signed-off-by: NLukasz Dalek <luk0104@gmail.com> Acked-by: NMarek Vasut <marex@denx.de>
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由 Jeroen Hofstee 提交于
cc: Tom Rini <trini@ti.com> Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl>
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由 Albert ARIBAUD 提交于
Run tools/reformat.py -i -d '-' -s 8 to reorder boards as header comments suggest
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由 Chin Liang See 提交于
Scan Manager driver will be called to configure the IOCSR scan chain. This configuration will setup the IO buffer settings Signed-off-by: NChin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
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由 Chin Liang See 提交于
To enable the DesignWare watchdog support at SOCFPGA Cyclone V dev kit. Signed-off-by: NChin Liang See <clsee@altera.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com>
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由 Chin Liang See 提交于
To add the DesignWare watchdog driver support. It required information such as register base address and clock info from configuration header file within include/configs folder. Signed-off-by: NChin Liang See <clsee@altera.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com>
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由 Sergey Kostanbaev 提交于
This patch returns back support for old ep93xx processors family Signed-off-by: NSergey Kostanbaev <sergey.kostanbaev@gmail.com> Cc: albert.u.boot@aribaud.net
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由 Axel Lin 提交于
In current gpio_set_value() implementation, it always sets the gpio control bit no matter the value argument is 0 or 1. Thus the GPIOs never set to low. This patch fixes this bug. The address bus is used as a mask on read/write operations, so that independent software drivers can set their GPIO bits without affecting any other pins in a single write operation. Thus we don't need a read-modify-write to update the register. Signed-off-by: NAxel Lin <axel.lin@ingics.com> Acked-by: NStefan Roese <sr@denx.de> Reviewed-by: NVipin Kumar <vipin.kumar@st.com> Reviewed-by: NMichael Trimarchi <michael@amarulasolutions.com>
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由 Jeroen Hofstee 提交于
This is not only more readable but also prevents a warning about a missing prototype. The prototypes which are actually missing are added. cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: NJeroen Hofstee <jeroen@myspectrum.nl> Reviewed-by: NTom Rini <trini@ti.com>
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由 York Sun 提交于
LS2085A is an ARMv8 implementation. This adds board support for emulator and simulator: Two DDR controllers UART2 is used as the console IFC timing is tightened for speedy booting Support DDR3 and DDR4 as separated targets Management Complex (MC) is enabled Support for GIC 500 (based on GICv3 arch) Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NArnab Basu <arnab.basu@freescale.com> Signed-off-by: NJ. German Rivera <German.Rivera@freescale.com> Signed-off-by: NBhupesh Sharma <bhupesh.sharma@freescale.com>
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- 03 7月, 2014 6 次提交
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由 J. German Rivera 提交于
Adding support to load and start the Layerscape Management Complex (MC) firmware. First, the MC GCR register is set to 0 to reset all cores. MC firmware and DPL images are copied from their location in NOR flash to DDR. MC registers are updated with the location of these images. Deasserting the reset bit of MC GCR register releases core 0 to run. Core 1 will be released by MC firmware. Stop bits are not touched for this step. U-boot waits for MC until it boots up. In case of a failure, device tree is updated accordingly. The MC firmware image uses FIT format. Signed-off-by: NJ. German Rivera <German.Rivera@freescale.com> Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NLijun Pan <Lijun.Pan@freescale.com> Signed-off-by: NShruti Kanetkar <Shruti@Freescale.com>
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由 York Sun 提交于
Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NVarun Sethi <Varun.Sethi@freescale.com> Signed-off-by: NArnab Basu <arnab.basu@freescale.com>
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由 York Sun 提交于
Make MMU function reusable. Platform code can setup its own MMU tables. Signed-off-by: NYork Sun <yorksun@freescale.com> CC: David Feng <fenghua@phytium.com.cn>
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由 J. German Rivera 提交于
This is needed for accessing peripherals with 64-bit MMIO registers, from ARMv8 processors. Signed-off-by: NJ. German Rivera <German.Rivera@freescale.com>
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由 Darwin Rambo 提交于
The armv8 ARM Trusted Firmware (ATF) can be used to load various ATF images and u-boot, and does this for virtual platforms by using semihosting. This commit extends this idea by allowing u-boot to also use semihosting to load the kernel/ramdisk/dtb. This eliminates the need for a bootwrapper and produces a more realistic boot sequence with virtual models. Though the semihosting code is quite generic, support for armv7 in fastmodel is less useful due to the wide range of available silicon and the lack of a free armv7 fastmodel, so this change contains an untested armv7 placeholder for the service trap opcode. Please refer to doc/README.semihosting for a more detailed description of semihosting and how it is used with the armv8 virtual platforms. Signed-off-by: NDarwin Rambo <drambo@broadcom.com> Cc: trini@ti.com Cc: fenghua@phytium.com.cn Cc: bhupesh.sharma@freescale.com
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