If including MX7D in CONFIG_SYS_EXTRA_OPTIONS, CONFIG_ROM_UNIFIED_SECTIONS
 will not effect.So move MX7D to Kconfig entry from CONFIG_SYS_EXTRA_OPTIONS to
"select MX7D" to boards using i.MX7 Dual.
Signed-off-by: NPeng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>

If including MX6SX in CONFIG_SYS_EXTRA_OPTIONS, CONFIG_ROM_UNIFIED_SECTIONS
will not effect.So move MX6SX to Kconfig entry from CONFIG_SYS_EXTRA_OPTIONS to
"select MX6SX" to boards using i.MX6 SoloX.
Signed-off-by: NPeng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>

This patch add support for the CCV xPress board which is equipped
with the i.MX6UL. And provides the following interfaces:

- 128MiB DDR
- UART
- I2C
- eMMC (with booting)
- Ethernet
- USB

This patch adds two build targets. One with and one without SPL. The
non-SPL version is used for loading U-Boot via USB (imx_usb_loader).
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>

Add the base address for the i.MX6UL so that this UART can be used.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>

Add the basic support for Warp7 board.

For more information about this reference design, please visit:

https://www.element14.com/community/docs/DOC-79058/l/warp-7-the-next-generation-wearable-reference-platformSigned-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: NPeng Fan <peng.fan@nxp.com>

CONFIG_BOARD_EARLY_INIT_F and CONFIG_BOARD_LATE_INIT should not be
placed into mx7_common because not all boards need these options.

Move them to the board file instead.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: NPeng Fan <peng.fan@nxp.com>

VESA 1024x768 results in much more accurate timings.

Based on the patch from Soeren Moch for the tbs2910 board.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>

Make the watchdog registers 16-bit wide, as they are according to TRM.
Signed-off-by: NLeonid Iziumtsev <leonid.iziumtsev@se.atlascopco.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>

Booting mx6qp sabreauto board and then doing:

=> saveenv
=> reset

, causes a system hang.

This happens because the size of the U-Boot binary is larger than
CONFIG_ENV_OFFSET.

Fix this problem by increasing CONFIG_ENV_OFFSET, so that the U-boot binary
and the environment variables region do not overlap.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>

Switch the DDR3 calibration from ad-hoc implementation of wait_for_bit()
to generic implementation of wait_for_bit().
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: NStefano Babic <sbabic@denx.de>

Enable NAND TrimFFS support in M53EVK, since it is convenient when
installing UBI images to NAND.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>

Default print ARM clock for clocks command.
Test on i.MX6UL 14x14 evk board:
"
=> clocks
PLL_SYS         792 MHz
PLL_BUS         528 MHz
PLL_OTG         480 MHz
PLL_NET          50 MHz

ARM          396000 kHz
"
Signed-off-by: NPeng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>

Configure the PMIC_STBY_REQ pin as open drain 100K according
to the design team's requirement for the PMIC_STBY_REQ pin
for i.MX 6UltraLite TO1.0.
Signed-off-by: NPeng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>

To i.MX6UL, default ARM rate and AHB rate is 396M and 198M,
no need to set them.
Signed-off-by: NPeng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>

Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register
the bit[17] for mmdc_ch0 is reserved and its proper state should be 1.
When clear this bit, the periph_clk_sel cannot be set and that
CDHIPR[periph_clk_sel_busy] handshake never clears.
Signed-off-by: NYe Li <ye.li@nxp.com>
Signed-off-by: NPeng Fan <van.freenix@gmail.com>
Acked-by: NStefano Babic <sbabic@denx.de>

Add some tests to check that block devices work as expected.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Tested-by: NStephen Warren <swarren@nvidia.com>

Driver model is used for host device block devices now, so we don't need the
old code. Remove it.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Tested-by: NStephen Warren <swarren@nvidia.com>

Now that the drivers used by sandbox support CONFIG_BLK, we can switch
sandbox over to use driver model for block devices.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Tested-by: NStephen Warren <swarren@nvidia.com>

When 'usb start' is used, block devices are created for any USB flash sticks
and disks, etc. When 'usb stop' is used, these block devices are currently
not removed.

We don't want old block devices hanging around since they can still be
visible to U-Boot. Therefore, when USB is shut down, remove and unbind all
the block devices created by the USB subsystem.

Possibly we should unbind all devices which don't cause problems by being
unbound. Most likely we can remove everything except USB controllers, hubs
and emulators. We can consider that later.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Tested-by: NStephen Warren <swarren@nvidia.com>

This option outputs to the log file, not to the terminal. Clarify that in
the help, and add a mention of it in the README.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reported-by: NStephen Warren <swarren@wwwdotorg.org>
Reviewed-by: NStephen Warren <swarren@nvidia.com>

At present buildman allows you to specify the directory containing the
toolchain, but not the actual toolchain prefix. If there are multiple
toolchains in a single directory, this can be inconvenient.

Add a new 'toolchain-prefix' setting to the settings file, which allows
the full prefix (or path to the C compiler) to be specified.

Update the documentation to match.
Suggested-by: NStephen Warren <swarren@wwwdotorg.org>
Reviewed-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NSimon Glass <sjg@chromium.org>
Tested-by: NStephen Warren <swarren@nvidia.com>

At present if you try to use buildman with the branch 'test' it will
complain that it is unsure whether you mean the branch or the directory.
This is a feature of the 'git log' command that buildman uses. Fix it
by resolving the ambiguity.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NJoe Hershberger <joe.hershberger@ni.com>

reg-offset is the part of standard 8250 binding in the kernel.
It is shifting start of address space by reg-offset.
On Xilinx platform this offset is typically 0x1000.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NTom Rini <trini@konsulko.com>
Moved the new field to the end of the struct to avoid problems:
Signed-off-by: NSimon Glass <sjg@chromium.org>

This reverts commit 71105f50.

The reverted commit was applied for a temporary to unbreak
few Exynos boards on the release.

After the discussion about the change, this commit should be avoided.
Fixed device-tree for Exynos, allows reverting it without any issues.
Signed-off-by: NPrzemyslaw Marczak <p.marczak@samsung.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: NSimon Glass <sjg@chromium.org>
Acked-by: NSimon Glass <sjg@chromium.org>

This change is required to avoid warnings about invalid
size-cells defined in device-tree pinctrl nodes for Exynos.

Tested on:
- Odroid U3
- Odroid XU3
Signed-off-by: NPrzemyslaw Marczak <p.marczak@samsung.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: NSimon Glass <sjg@chromium.org>
Acked-by: NSimon Glass <sjg@chromium.org>
Acked-by: NMinkyu Kang <mk7.kang@samsung.com>

Some controllers do not allow the output value to be read. Detect this and
report the error in that case.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Since dhry_per_sec is a u64 we must also use lldiv here when working
with it.  Otherwise:
../lib/dhry/cmd_dhry.c:(.text.do_dhry+0xd8): undefined reference to `__udivdi3'

On some platforms.
Signed-off-by: NTom Rini <trini@konsulko.com>

This patch adds support for the congatec conga-QA3/E3845-4G eMMC8 SoM,
installed on the congatec Qseven 2.0 evaluation carrier board
(conga-QEVAL).

Its port is very similar to the MinnowboardMAX port and also uses
the Intel FSP as described in doc/README.x86.

Currently supported are the following interfaces / devices:
- UART (via Winbond legacy SuperIO chip on carrier board)
- Ethernet (PCIe Intel I210 / E1000)
- SPI including SPI NOR as boot-device
- USB 2.0
- SATA via U-Boot SCSI IF
- eMMC
- Video (HDMI output @ 800x600)
- PCIe

Not supported yet is:
- I2C
- USB 3.0
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

This adds basic support for chromebook_samus. This is the 2015 Pixel and
is based on an Intel broadwell platform.

Supported so far are:
- Serial
- SPI flash
- SDRAM init (with MRC cache)
- SATA
- Video (on the internal LCD panel)
- Keyboard

Various less-visible drivers are provided to make the above work (e.g. PCH,
power control and LPC).

The platform requires various binary blobs which are documented in the
README. The major missing feature is USB3 since the existing U-Boot support
does not work correctly with Intel XHCI controllers.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Sometimes it is useful to jump into U-Boot directly from coreboot or UEFI
without any 16-bit init. This can help during development by allowing U-Boot
to avoid doing all the init required by the platform.

U-Boot expects its GDT to be set up correctly by its 16-bit code. If
coreboot doesn't do this (because it hasn't run the payload setup code yet)
then this won't happen.

In this case we cannot rely on the GDT settings. U-Boot will hang or crash
if these are wrong. Provide a development-only option to set up the GDT
correctly. This is just a hack so you can jump to U-Boot from any stage of
coreboot, not just at the end.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

This is not needed now that the memory controller driver has the SPD data
in its own node.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Adjust the existing implementation to use the new common SDRAM init code.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

The code to call the memory reference code is common to several Intel CPUs.
Add common code for performing this init. Intel calls this 'Pre-EFI-Init'
(PEI), where EFI stands for Extensible Firmware Interface.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

The SATA indexed register write functions are common to several Intel PCHs.
Move this into a common location.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

At present samus reports about 5600 DMIPS. With the default iteration count
this is OK, but if 10 million runs are performed it overflows. Fix it.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This is missing, with causes lldiv() to fail on boards with use the private
libgcc. Add the missing routine.

Code is available for using the CLZ instruction but it is not enabled at
present.

This comes from coreboot version 4.0.
Signed-off-by: NSimon Glass <sjg@chromium.org>

There is an extra line in the comment in the header. Remove it.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Add a function to set the ID in the IOAPIC.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Update a few points which have become out-of-date.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>