As per updated board design, different QSPI flash
is connected on boards, hence change QSPI flash type
from Micron n25q512a device to spansion s25fs512s
device in dts and config.
Signed-off-by: NSantan Kumar <santan.kumar@nxp.com>
Signed-off-by: NYogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

CONFIG_DISPLAY_BOARDINFO_LATE config is used to delay
the prints of boardinfo late in cycle during uboot boot.
This feature is not required in case of QSPI_BOOT.
Signed-off-by: NSantan Kumar <santan.kumar@nxp.com>
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

It is not necessary for every SoC to have 2 SATA controller.
So put SATA1, SATA2 code under respective defines.
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Commit a8ecb39e accidentally reverted config macro CONFIG_ARCH_LS1021A
to CONFIG_LS102XA.
Signed-off-by: NYork Sun <york.sun@nxp.com>

Our minimum DTC version is 1.4.3, so check that out.
Signed-off-by: NTom Rini <trini@konsulko.com>

Fixes:
net/tftp.c:811: undefined reference to `efi_set_bootdev'
Signed-off-by: NJörg Krause <joerg.krause@embedded.rocks>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

With support for overlays and calling the -@ flag to dtc we need to have
at least 1.4.3 available now.

Cc: Simon Glass <sjg@chromium.org>
Reported-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NTom Rini <trini@konsulko.com>

common/spl/spl_fit.c:201:12: warning: passing argument 4 of ‘gunzip’
from incompatible pointer type [-Wincompatible-pointer-types]
       src, &length))
Signed-off-by: NYork Sun <york.sun@nxp.com>
Reported-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
CC: Jean-Jacques Hiblot <jjhiblot@ti.com>

This patch provides default implementations of the two functions
set_uart_mux_conf and set_mux_conf_regs. Hence boards not using
them do not need to provide their distinct empty definitions.
Signed-off-by: NFelix Brack <fb@ltec.ch>
Reviewed-by: NTom Rini <trini@konsulko.com>

This patch adds support for stm32h7 soc family, stm32h743
discovery and evaluation boards.

For more information about STM32H7 series, please visit:
http://www.st.com/en/microcontrollers/stm32h7-series.htmlSigned-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This patch adapts stm32h743 disco and eval dts files to match
with U-boot requirements or add features wich are not yet
upstreamed on kernel side :

_ Add RCC clock driver node and update all clocks phandle
  accordingly.

  By default, on kernel side, all clocks was temporarly
  configured as a phandle to timer_clk waiting for a RCC
  clock driver to be available.
  On U-boot side, we now have a dedicated RCC clock driver, we
  can configured all clocks as phandle to this driver.

  All this binding update will be available soon in a kernel tag,
  as all the bindings have been acked by Rob Herring [1].

  [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html

_ Align STM32H7 serial compatible string with the one which will be
  available in next kernel tag. The bindings has been acked by
  Rob Herring [2].
  This compatible string will be usefull to add stm32h7 specific
  feature for this serial driver.

  [2] https://lkml.org/lkml/2017/7/17/739

_ Add gpio compatible and aliases for stm32h743

_ Add FMC sdram node with associated new bindings value to
  manage second bank (ie bank 1).

_ Add missing HSI and CSI oscillators nodes needed
  by STM32H7 RCC clock driver.

  Clock sources could be:
	_ HSE (High Speed External)
	_ HSI (High Speed Internal)
	_ CSI (Low Power Internal)

  These clocks can be used as clocksource in some configuration.
  By default, HSE is selected as clock source.

_ Set HSE to 25Mhz for stm32h743i-disco and eval board

  By default, the external oscillator frequency is defined at
  25 Mhz in SoC stm32h743.dtsi file.
  It has been set at 125 Mhz in kernel DT temporarly waiting for
  RCC clock driver becomes available.

  As in U-boot we got a RCC clock driver, the real value of HSE
  clock can be used.

_ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl,
  pwrcfg and gpio nodes.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This file is imported from linux kernel v4.13

Add device tree support for STM32H743 evaluation board.
This board offers :
  _ STM32H743XIH6 microcontroller with 2 Mbytes of
    Flash memory and 1 Mbyte of RAM in TFBGA240+25 package
  _ 5.7” 640x480 TFT color LCD with touch screen
  _ Ethernet compliant with IEEE-802.3-2002
  _ USB OTG HS and FS
  _ I2 C compatible serial interface
  _ RTC with rechargeable backup battery
  _ SAI Audio DAC
  _ ST-MEMS digital microphones
  _ 8-Gbyte (or more) SDIO3.0 interface microSD™ card
  _ 8Mx32bit SDRAM, 1Mx16bit SRAM and 8Mx16bit NOR Flash
  _ 1-Gbit Twin Quad-SPI NOR Flash
  _ Potentiometer
  _ 4 colored user LEDs
  _ Reset, wakeup, tamper or key buttons
  _ Joystick with 4-direction control and selector
  _ Board connectors :
     Power jack
     3 USB with Micro-AB
     RS-232 communications
     Ethernet RJ45
     FD-CAN compliant connection
     Stereo headset jack including analog microphone input
     2 audio jacks for external speakers
     microSD™ card
     JTAG/SWD and ETM trace
   _ Expansion connectors:
     Extension connectors and memory connectors for daughterboard
     or wire-wrap board
   _ Flexible power-supply options: ST-LINK USB VBUS or external
     sources
   _ On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration
     capability: mass storage, virtual COM port and debug port
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

All these files are imported from linux kernel v4.13

Add device tree support for STM32H743 SoC and discovery
board. This board offers :
  _ STM32H743XIH6 microcontroller with 2 Mbytes of
    Flash memory and 1 Mbyte of RAM in TFBGA240+25 package
  _ 5.7” 640x480 TFT color LCD with touch screen
  _ Ethernet compliant with IEEE-802.3-2002
  _ USB OTG HS
  _ I2 C compatible serial interface
  _ ST-MEMS digital microphones
  _ 8-Gbyte (or more) SDIO3.0 interface microSD™ card
  _ 8Mx32bit SDRAM
  _ 1-Gbit Twin Quad-SPI NOR Flash
  _ Reset, wakeup, or key buttons
  _ Joystick with 4-direction control and selector
  _ Board connectors :
	1 USB with Micro-AB
	Ethernet RJ45
	Stereo headset jack including analog microphone input
	microSD™ card
	RCA connector
	JTAG/SWD and ETM trace
   _ Expansion connectors:
	Arduino Uno compatible Connectors
	2 x PIO connectors (PMOD and PMOD+)
   _ On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration
     capability: mass storage, virtual COM port and debug port
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NVikas Manocha <vikas.manocha@st.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This patch adds the support of reset and clock control
block (rcc) found on STM32 SoCs.
This driver is similar to a MFD linux driver.

This driver supports currently STM32H7 only.
STM32F4 and STM32F7 will be migrated to this rcc MFD driver
in the future to uniformize all STM32 SoCs already upstreamed.
Signed-off-by: NChristophe Kerello <christophe.kerello@st.com>
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NVikas Manocha <vikas.manocha@st.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This driver is adapted from linux drivers/reset/reset-stm32.c
It's compatible with STM32 F4/F7/H7 SoCs.

This driver doesn't implement .of_match as it's binded
by MFD RCC driver.

To add support for each SoC family, a SoC's specific
include/dt-binfings/mfd/stm32xx-rcc.h file must be added.

This patch only includes stm32h7-rcc.h dedicated for STM32H7 SoCs.
Other SoCs support will be added in the future.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This driver implements basic clock setup, only clock gating
is implemented.

This driver doesn't implement .of_match as it's binded
by MFD RCC driver.

Files include/dt-bindings/clock/stm32h7-clks.h and
doc/device-tree-bindings/clock/st,stm32h7-rcc.txt
will be available soon in a kernel tag, as all the
bindings have been acked by Rob Herring [1].

[1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.htmlSigned-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

STM32F7 and STM32H7 shares the same UART block, add
STM32H7 compatible string.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

STM32H7 SoCs uses the same pinctrl block as found into
STM32F7 SoCs
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NVikas Manocha <vikas.manocha@st.com>

Since we may jump to next stage like ATF/OP-TEE instead of U-Boot,
we need to stash the bootstage info before it.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Add usb_gadget_handle_interrupts(), board_usb_init(),
board_usb_cleanup() and g_dnl_board_usb_cable_connected()
callbacks needed for FASTBOOT support
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Update ehci and ohci node's compatible string in order to
use ehci-generic and ohci-generic drivers.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

On STi 96boards, configure by default the micro USB connector
(managed by DWC3 hardware block) in peripheral mode.
This will allow to use fastboot feature.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This patch adds the ST glue logic to manage the DWC3 HC
on STiH407 SoC family. It configures the internal glue
logic and syscfg registers.

Part of this code been extracted from kernel.org driver
(drivers/usb/dwc3/dwc3-st.c)
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Enable USB Host Networking support by enabling Ethernet/USB
adaptors support and by enabling some BOOTP flags
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This is the generic phy driver for the picoPHY ports
used by USB2/1.1 controllers. It is found on STiH407 SoC
family from STMicroelectronics.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

reset-names property is needed to use the reset
API for STi sdhci driver.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Use struct udevice* as input parameter. Previous
parameters are retrieved through plat and priv data.

This to prepare to use the reset framework.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

'default n' is the default anyway so it doesn't need to be specified
explicitly, and the rest of the file doesn't specify it either anywhere.
Drop it.
Signed-off-by: NTuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

This field is no longer used since the DM conversion. Drop it.
Signed-off-by: NTuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

This field is no longer used since the DM conversion. Drop it.
Signed-off-by: NTuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

This field has never been used as the driver has been DM-based since the
beginning. Drop it.
Signed-off-by: NTuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

These take the 'struct udevice *' as an argument, not the
'struct xilinx_pcie *` which is a local variable. Fix the comments to
match the code.
Signed-off-by: NTuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

We have limited stack in SPL builds.  Drop itrblock and move to
malloc/free of itr to move this off of the stack.  As part of this fix a
double-free issue in fat_size().
Signed-off-by: NTom Rini <trini@konsulko.com>
---
Rework to use malloc/free as moving this to a global overflows some SH
targets.

Support spi driver and can detect MX25U1635E flash on AE3XX board.

Verification:

sf probe 0:0 50000000 0
spi_flash_std_probe(sf_Probr.c)
	spi_flash_probe_slave(sf_Probr.c)
	SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
	NDS32 # sf test 0x100000 0x1000
	SPI flash test:
	0 erase: 34 ticks, 117 KiB/s 0.936 Mbps
	1 check: 15 ticks, 266 KiB/s 2.128 Mbps
	2 write: 21 ticks, 190 KiB/s 1.520 Mbps
	3 read: 11 ticks, 363 KiB/s 2.904 Mbps
	Test passed
	0 erase: 34 ticks, 117 KiB/s 0.936 Mbps
	1 check: 15 ticks, 266 KiB/s 2.128 Mbps
	2 write: 21 ticks, 190 KiB/s 1.520 Mbps
	3 read: 11 ticks, 363 KiB/s 2.904 Mbps
Signed-off-by: Nrick <rick@andestech.com>

Add spi dts node and enable spi dm flash config.
Signed-off-by: Nrick <rick@andestech.com>

To support MACRONIX MX25U1635E 16M-BIT flash.
Signed-off-by: Nrick <rick@andestech.com>

After soft reset complete, write mac address immediately will fail.
Add delay to work around this problem.
Signed-off-by: Nrick <rick@andestech.com>