Follow Linux commit ed067d4a859f ("linux/kernel.h: Add ALIGN_DOWN
macro").
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The following config symbols are only defined once and never referenced
anywhere else:

CONFIG_AP325RXA
CONFIG_AP_SH4A_4A
CONFIG_CPU_SH_TYPE_R
CONFIG_ECOVEC
CONFIG_ESPT
CONFIG_MIGO_R
CONFIG_MPR2
CONFIG_MS7720SE
CONFIG_MS7722SE
CONFIG_MS7750SE
CONFIG_R0P7734
CONFIG_R2DPLUS
CONFIG_RSK7203
CONFIG_RSK7264
CONFIG_RSK7269
CONFIG_SH7752EVB
CONFIG_SH7753EVB
CONFIG_SH7757LCR
CONFIG_SH7763RDP
CONFIG_SH7785LCR

Most of them are config symbols named after the respective boards which
seems to have been a standard practice at some point.
Signed-off-by: NTuomas Tynkkynen <tuomas@tuxera.com>

These macros are all defined once and never checked or used anywhere:

CONFIG_MACH_ASPENITE
CONFIG_MACH_DAVINCI_CALIMAIN
CONFIG_MACH_DOCKSTAR
CONFIG_MACH_EDMINIV2
CONFIG_MACH_GOFLEXHOME
CONFIG_MACH_GONI
CONFIG_MACH_GURUPLUG
CONFIG_MACH_KM_KIRKWOOD
CONFIG_MACH_OPENRD_BASE
CONFIG_MACH_SHEEVAPLUG

Almost all of them were only used for the mach_is_foo() logic in
arch/arm/asm/mach-types.h that were dropped in
commit f9dadaef ("arm: Re-sync asm/mach-types.h with
Linux Kernel v4.9")
Signed-off-by: NTuomas Tynkkynen <tuomas@tuxera.com>

Configure AM57xx EVMs for the exact PHY part that is
present on the various boards. This makes U-Boot apply
configurations needed for this PHY like centering the
FLP timing.

For configurations to take effect, DM_ETH needs to be
enabled. Do that too.

Tested on BeagleBoard x15 and AM571x IDK.
Reviewed-by: NLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

The 't208xrdb t4qds t102*' job is close to the time limit and
sometimes fails, so this splits it into 3 separate jobs.
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

Last user of this option went away in 2015 in commit:
d928664f ("powerpc: 74xx_7xx: remove 74xx_7xx cpu support")
Signed-off-by: NTuomas Tynkkynen <tuomas@tuxera.com>

BCM2835 ARM Peripherals doc shows gpio pins 4, 5, 6, 12 and 13 carry altenate
function, ALT5 for ARM JTAG
Signed-off-by: NHenry Zhang <henryzhang62@yahoo.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

STM32F469-disco embeds an arm_pl180 mmc IP, so
enable CMD_MMC, DM_MMC and ARM_PL180_MMCI flags.

Also enables all filesystem command related flags :
  _ CMD_EXT2
  _ CMD_EXT4
  _ CMD_FAT
  _ CMD_FS_GENERIC
  _ CMD_GPT
  _ CMD_BOOTZ
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Add DT nodes to enable ARM_PL180_MMCI IP support for STM32F746
and STM32F769 discovery boards

There is a hardware issue on these boards, it misses a pullup on the GPIO line
used as card detect to allow correct SD card detection.
As workaround, cd-gpios property is not present in DT.
So SD card is always considered present in the slot.
Signed-off-by: NChristophe Priouzeau <christophe.priouzeau@st.com>
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

STM32F469 SoC uses an arm_pl180_mmci SDIO controller.
Signed-off-by: NAndrea Merello <andrea.merello@gmail.com>
Signed-off-by: NAlexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

This board offers :

 _ STM32F469NIH6 microcontroller featuring 2 Mbytes of Flash memory
   and 324 Kbytes of RAM in BGA216 package
 _ On-board ST-LINK/V2-1 SWD debugger, supporting USB reenumeration capability:
     _ Mbed-enabled (mbed.org)
     _ USB functions: USB virtual COM port, mass storage, debug port
 _ 4 inches 800x480 pixel TFT color LCD with MIPI DSI interface and capacitive
   touch screen
 _ SAI Audio DAC, with a stereo headphone output jack
 _ 3 MEMS microphones
 _ MicroSD card connector
 _ I2C extension connector
 _ 4Mx32bit SDRAM
 _ 128-Mbit Quad-SPI NOR Flash
 _ Reset and wake-up buttons
 _ 4 color user LEDs
 _ USB OTG FS with Micro-AB connector
 _ Three power supply options:
 _ Expansion connectors and Arduino™ UNO V3 connectors
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

  _ Add gpio compatible and aliases for stm32f469

  _ Add FMC sdram node

  _ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl,
    pwrcfg and gpio nodes.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

This DT file comes from kernel v4.15-rc1

stm32f469-pinctrl.dtsi header has been updated with correct
STMicroelectronics Copyright.

Remove the paragraph about writing to the Free Software
Foundation's mailing address as requested by checkpatch.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

This allows to controls the memory internal mapping at
address 0x0000 0000.
We can either map at 0x0000 0000 :
  _ main flash memory
  _ system flash memory
  _ FMC bank1 (NOR/PSRAM 1 and 2)
  _ embedded SRAM
  _ FMC/SDRAM bank1

This is needed for future STM32F469-disco board
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

Use available DM stm32f7_gpio.c and pinctrl_stm32.c drivers
instead of board GPIO initialization.

Remove stm32_gpio.c which is no more used and migrate
structs stm32_gpio_regs and stm32_gpio_priv into
arch-stm32f4/gpio.h to not break compilation.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

Use available DM clk_stm32f.c driver instead of dedicated
mach-stm32/stm32f4/clock.c.

Migrate periph_clock defines from stm32_periph.h directly in
CLK driver. These periph_clock defines will be removed when STMMAC,
TIMER2 and SYSCFG drivers will support DM CLK.

Enable also CLK flag.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

In order to use common clock driver between STM32F4 and
STM32F7, remove clock_get() call
As APB_PSC is always set to 2, only case when
clock_get(CLOCK_AHB) != clock_get(CLOCK_APB1) is kept
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

Remove serial_stm32.c driver and uart init from board file,
use available DM serial_stm32x7.c driver compatible for
STM32F4/F7 and H7 SoCs.

The serial_stm32x7.c driver will be renamed later with a more
generic name as it's shared with all STM32 Socs.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

This allows to support rcc MFD driver.
By enabling all these flags, we need to increase malloc area to avoid
crash during early stage.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

STM32F4 SoCs uses the same pinctrl block as found into
STM32F7 and H7 SoCs.
We can add "st,stm32f429-pinctrl" and "st,stm32f469-pinctrl"
compatible string into pinctrl_stm32.c.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

Use available DM stm32_sdram.c driver instead of board
SDRAM initialization.
For that, enable OF_CONTROL, OF_EMBED and STM32_SDRAM flags.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

_ Add gpio compatible and aliases for stm32f429

_ Add FMC sdram node with associated new bindings value to
  manage second bank (ie bank 1).

_ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl,
  pwrcfg and gpio nodes.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

All these files comes from kernel v4.15-rc1.

Update some header with correct STMicroelectronics Copyright.

Remove the paragraph about writing to the Free Software
Foundation's mailing address as requested by checkpatch.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

By applying this patch, we are ensuring that the code paths
responsible for applying errata workarounds are also exercised
on CPU revisions, which actually don't need these workarounds.

Only CONFIG_ARM_ERRATA_621766, CONFIG_ARM_ERRATA_454179,
CONFIG_ARM_ERRATA_725233 and CONFIG_ARM_ERRATA_430973 are
covered by this patch (Cortex-A8).

This improves code coverage when testing U-Boot builds
on newer hardware. In particular, the problematic commit
00bbe96e ("arm: omap: Unify get_device_type() function")
would break both BeageBoard and BeagleBoard XM rather than
just older BeagleBoard.

As an additional bonus, we need fewer instructins and the SPL
size is reduced.
Signed-off-by: NSiarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

I do not see a good reason to do this by a CONFIG option that affects
all SoCs.  The ram_size can be adjusted by dram_init() at run-time.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

I did not enable SDMA when I added sdhci-cadence support because LD20
boards are equipped with a large amount memory beyond 32 bit address
range, but SDMA does not support the 64bit address.  U-Boot relocates
itself to the end of effectively available RAM.  This would make the
MMC enumeration fail because the buffer for EXT_CSD allocated in the
stack would go too high, then SDMA would fail to transfer data.

Recent SDHCI-compatible controllers support ADMA, but unfortunately
U-Boot does not support ADMA.

In the previous commit, I hided the DRAM area that exceeds the 32 bit
address range.  Now, I can enable CONFIG_MMC_SDHCI_SDMA.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

LD20 / PXs3 boards are equipped with a large amount of memory beyond
the 32 bit address range.  U-Boot relocates itself to the end of the
available RAM.

This is a problem for DMA engines that only support 32 bit physical
address, like the SDMA of SDHCI controllers.

In fact, U-Boot does not need to run at the very end of RAM.  It is
rather troublesome for drivers with DMA engines because U-Boot does
not have API like dma_set_mask(), so DMA silently fails, making the
driver debugging difficult.

Hide the memory region that exceeds the 32 bit address range.  It can
be done by simply carving out gd->ram_size.  It would also possible to
override get_effective_memsize() or to define CONFIG_MAX_MEM_MAPPED,
but dram_init() is a good enough place to do this job.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Bind rockchip reset to clock-controller with rockchip_reset_bind().
Signed-off-by: NElaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

Create driver to support the soft reset (i.e. peripheral)
of all Rockchip SoCs.

Example of usage:
i2c driver:
	ret = reset_get_by_name(dev, "i2c", &reset_ctl);
	if (ret) {
		error("reset_get_by_name() failed: %d\n", ret);
	}

	reset_assert(&reset_ctl);
	udelay(50);
	reset_deassert(&reset_ctl);

i2c dts node:
resets = <&cru SRST_P_I2C1>, <&cru SRST_I2C1>;
reset-names = "p_i2c", "i2c";
Signed-off-by: NElaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Acked-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Fixed commit tag:]
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

Signed-off-by: NTom Rini <trini@konsulko.com>

It is not much needed to print nand size in SPL during nand boot,
and most of nand spl drivers doesn't print the same.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

board/icorem6_rqs/ is forgot to remove while moving
common board files together in
(sha1: 52aaddd6)
"i..MX6: engicam: Add imx6q/imx6ul boards for existing boards"
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

The i.MX 6UL/ULL feature a Cortex-A7 CPU which suppor the ARM
generic timer. This change makes use of the ARM generic timer in
U-Boot.

This is crucial to make the ARM generic timers usable in Linux since
timer_init() initalizes the system counter module, which is necessary
to use the generic timers CP15 registers.
Signed-off-by: NStefan Agner <stefan.agner@toradex.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>

Introduce a new config symbol to select the i.MX
General Purpose Timer (GPT).
Signed-off-by: NStefan Agner <stefan.agner@toradex.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>

Signed-off-by: NStefan Agner <stefan.agner@toradex.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>

The blob_encap and blob_decap functions were not flushing the dcache
before passing data to CAAM/DMA and not invalidating the dcache when
getting data back.
Therefore, blob encapsulation and decapsulation failed with errors like
the following due to data cache incoherency:
"40000006: DECO: desc idx 0: Invalid KEY command"

To ensure coherency, we require the key_mod, src and dst buffers to be
aligned to the cache line size and flush/invalidate the memory regions.
The same requirements apply to the job descriptor.

Tested on an i.MX6Q board.
Reviewed-by: NSumit Garg <sumit.garg@nxp.com>
Signed-off-by: NClemens Gruber <clemens.gruber@pqgruber.com>