1. 25 11月, 2014 1 次提交
  2. 23 11月, 2014 28 次提交
  3. 21 11月, 2014 11 次提交
    • S
      x86: Rename chromebook-x86 to coreboot · fe5b9b44
      Simon Glass 提交于
      Rename this vendor since it is intended to be used on any platform where
      coreboot runs at reset and then loads U-Boot.
      
      So far it is only tested on link. When other boards are supported it is
      likely that we will need to move to multiple board names, all under the
      'coreboot' vendor. So while it would be possible to remove the vendor for
      now, that would be short-sighted.
      Suggested-by: NBin Meng <bmeng.cn@gmail.com>
      Signed-off-by: NSimon Glass <sjg@chromium.org>
      fe5b9b44
    • S
      x86: ivybridge: Implement SDRAM init · 65dd74a6
      Simon Glass 提交于
      Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in
      the board directory and the SDRAM SPD information in the device tree. This
      also needs the Intel Management Engine (me.bin) to work. Binary blobs
      everywhere: so far we have MRC, ME and microcode.
      
      SDRAM init works by setting up various parameters and calling the MRC. This
      in turn does some sort of magic to work out how much memory there is and
      the timing parameters to use. It also sets up the DRAM controllers. When
      the MRC returns, we use the information it provides to map out the
      available memory in U-Boot.
      
      U-Boot normally moves itself to the top of RAM. On x86 the RAM is not
      generally contiguous, and anyway some RAM may be above 4GB which doesn't
      work in 32-bit mode. So we relocate to the top of the largest block of
      RAM we can find below 4GB. Memory above 4GB is accessible with special
      functions (see physmem).
      
      It would be possible to build U-Boot in 64-bit mode but this wouldn't
      necessarily provide any more memory, since the largest block is often below
      4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large
      ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit
      kernels directly so this does not pose a limitation in that area. Also there
      are probably parts of U-Boot that will not work correctly in 64-bit mode.
      The MRC is one.
      
      There is some work remaining in this area. Since memory init is very slow
      (over 500ms) it is possible to save the parameters in SPI flash to speed it
      up next time. Suspend/resume support is not fully implemented, or at least
      it is not efficient.
      
      With this patch, link boots to a prompt.
      Signed-off-by: NSimon Glass <sjg@chromium.org>
      65dd74a6
    • S
      x86: ivybridge: Add LAPIC support · 3eafce05
      Simon Glass 提交于
      The local advanced programmable interrupt controller is not used much in
      U-Boot but we do need to set it up. Add basic support for this, which will
      be extended as needed.
      Signed-off-by: NSimon Glass <sjg@chromium.org>
      3eafce05
    • S
      x86: Make show_boot_progress() common · a49e3c7f
      Simon Glass 提交于
      This function can probably be used on all x86 boards, so move it into the
      common file.
      Signed-off-by: NSimon Glass <sjg@chromium.org>
      a49e3c7f
    • S
      x86: chromebook_link: Enable GPIO support · 437c2b7c
      Simon Glass 提交于
      Enable GPIO support and provide the required GPIO setup information to
      the driver.
      Signed-off-by: NSimon Glass <sjg@chromium.org>
      437c2b7c
    • S
      x86: ivybridge: Add support for early GPIO init · 1b4f25ff
      Simon Glass 提交于
      When not relying on Coreboot for GPIO init the GPIOs must be set up
      correctly. This is currently done statically through a rather ugly method.
      As the GPIOs are figured out they can be moved to the device tree and set
      up as needed rather than all at the start.
      
      In this implementation, board files should call ich_gpio_set_gpio_map()
      before the GPIO driver is used in order to provide the GPIO information.
      We use the early PCI interface so that this driver can now be used before
      relocation.
      Signed-off-by: NSimon Glass <sjg@chromium.org>
      1b4f25ff
    • S
      x86: ivybridge: Add early init for PCH devices · 8e0df066
      Simon Glass 提交于
      Many PCH devices are hard-coded to a particular PCI address. Set these
      up early in case they are needed.
      Signed-off-by: NSimon Glass <sjg@chromium.org>
      8e0df066
    • S
      x86: dts: Add microcode updates for ivybridge CPU · 9c678e15
      Simon Glass 提交于
      Add two microcode updates that are provided for this CPU. The updates
      have been converted to a device tree form.
      
      Note: SPDX submission has been done. If this license is approved I will
      convert the files to use SPDX.
      Signed-off-by: NSimon Glass <sjg@chromium.org>
      9c678e15
    • S
      x86: ivybridge: Perform Intel microcode update on boot · 77f9b1fb
      Simon Glass 提交于
      Microcode updates are stored in the device tree. Work through these and
      apply any that are needed.
      Signed-off-by: NSimon Glass <sjg@chromium.org>
      77f9b1fb
    • S
      x86: ivybridge: Check BIST value on boot · 94060ff2
      Simon Glass 提交于
      The built-in self test value should be checked before we continue booting.
      Refuse to continue if there is something wrong.
      Signed-off-by: NSimon Glass <sjg@chromium.org>
      94060ff2
    • S
      x86: ivybridge: Perform initial CPU setup · f5fbbe95
      Simon Glass 提交于
      Set up the flex ratio (controls speed versus heat output) and a few other
      very early things.
      Signed-off-by: NSimon Glass <sjg@chromium.org>
      f5fbbe95