- 28 4月, 2011 24 次提交
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由 Tom Warren 提交于
Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Luca Ceresoli 提交于
Signed-off-by: NLuca Ceresoli <luca.ceresoli@comelit.it> Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>
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由 Luca Ceresoli 提交于
CONFIG_OMAP34XX must be checked for existence, not value. Signed-off-by: NLuca Ceresoli <luca.ceresoli@comelit.it> Cc: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.aribaud@free.fr> Cc: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>
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由 Alexander Holler 提交于
The reset sequence/configuration for ehci is highly board specific, so this will be done in the source for the board, instead of introducing several CONFIG_* which would be needed to make those few lines in beagle.c usable across different OMAP boards. Signed-off-by: NAlexander Holler <holler@ahsoftware.de> Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>
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由 Alexander Holler 提交于
Signed-off-by: NAlexander Holler <holler@ahsoftware.de> Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>
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由 Albert ARIBAUD 提交于
Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net>
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由 Macpaul Lin 提交于
Fix include path of timer fttmr010 in a320evb. Signed-off-by: NMacpaul Lin <macpaul@andestech.com>
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由 Macpaul Lin 提交于
Move the header file and definitions of fttmr010 power control unit from a320 SoC folder to "include/faraday" folder. This change will let other SoC which also use fttmr010 could share the same header file. Signed-off-by: NMacpaul Lin <macpaul@andestech.com>
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由 Rogan Dawes 提交于
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由 Lei Wen 提交于
Add i2c support to aspenite board with Armada100 soc. Acked-by: NHeiko Schocher <hs@denx.de> Acked-by: NPrafulla Wadaskar <prafulla@marvell.com> Signed-off-by: NLei Wen <leiwen@marvell.com>
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由 Lei Wen 提交于
Add i2c support to dkb board with pantheon soc. Acked-by: NHeiko Schocher <hs@denx.de> Acked-by: NPrafulla Wadaskar <prafulla@marvell.com> Signed-off-by: NLei Wen <leiwen@marvell.com>
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由 Lei Wen 提交于
Add i2c_clk_enable in the cpu specific code, since previous platform it, while new platform don't need. In the pantheon and armada100 platform, this function is defined as NULL one. Acked-by: NHeiko Schocher <hs@denx.de> Acked-by: NPrafulla Wadaskar <prafulla@marvell.com> Signed-off-by: NLei Wen <leiwen@marvell.com>
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由 Lei Wen 提交于
For better sharing with other platform other than pxa's, it is more convenient to put the driver to the common place. Acked-by: NHeiko Schocher <hs@denx.de> Acked-by: NPrafulla Wadaskar <prafulla@marvell.com> Signed-off-by: NLei Wen <leiwen@marvell.com>
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由 Po-Yu Chuang 提交于
ftpmu010 related code has been moved to drivers/power/. Signed-off-by: NPo-Yu Chuang <ratbert@faraday-tech.com> Signed-off-by: NAlbert Aribaud <albert.aribaud@free.fr>
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由 Matthias Weisser 提交于
Using optimized versions of memset and memcpy from linux brings a quite noticeable speed (x2 or better) improvement for these two functions. Here are some numbers for test done with jadecpu | HEAD(1)| HEAD(1)| HEAD(2)| HEAD(2)| | | +patch | | +patch | ---------------------------+--------+--------+--------+--------+ Reset to prompt | 438ms | 330ms | 228ms | 120ms | | | | | | TFTP a 3MB img | 4782ms | 3428ms | 3245ms | 2820ms | | | | | | FATLOAD USB a 3MB img* | 8515ms | 8510ms | ------ | ------ | | | | | | BOOTM LZO img in RAM | 3473ms | 3168ms | 592ms | 592ms | where CRC is | 615ms | 615ms | 54ms | 54ms | uncompress | 2460ms | 2462ms | 450ms | 451ms | final boot_elf | 376ms | 68ms | 65ms | 65ms | | | | | | BOOTM LZO img in FLASH | 3207ms | 2902ms | 1050ms | 1050ms | where CRC is | 600ms | 600ms | 135ms | 135ms | uncompress | 2209ms | 2211ms | 828ms | 828ms | | | | | | Copy 1.4MB from NOR to RAM | 134ms | 72ms | 120ms | 70ms | (1) No dcache (2) dcache enabled in board_init *Does not work when dcache is on Size impact: C version: text data bss dec hex filename 202862 18912 266456 488230 77326 u-boot ASM version: text data bss dec hex filename 203798 18912 266288 488998 77626 u-boot 222712 u-boot.bin Signed-off-by: NMatthias Weisser <weisserm@arcor.de>
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由 Steve Kipisz 提交于
This allows the reading of EEPROMS on the expansion bus without adding external pull-ups. Signed-off-by: NJason Kridner <jkridner@beagleboard.org> Signed-off-by: NSteve Kipisz <s-kipisz2@ti.com> Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>
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由 Stefano Babic 提交于
Drop warnings due to recent commit ARM: mx31: Print the silicon version Signed-off-by: NStefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com>
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由 Jason Liu 提交于
factor out boot cause function to common code to avoid the duplicate code in each board support package Signed-off-by: NJason Liu <jason.hui@linaro.org>
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由 Fabio Estevam 提交于
Commit 5d2c154 (IMX: MX31: Cleanup include files and drop nasty #ifdef in drivers) renamed mx31-imx-regs.h to imx-regs.h. Change the file label accordingly. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
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由 Fabio Estevam 提交于
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Acked-by: NDetlev Zundel <dzu@denx.de>
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由 Fabio Estevam 提交于
Use the same method of the Linux kernel to print the MX31 silicon version on boot. Tested on a MX31PDK with a 2.0 silicon, where it shows: CPU: Freescale i.MX31 rev 2.0 at 531 MHz Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
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由 Stefano Babic 提交于
As exception among the i.MX processors, the i.MX31 has headers without general names (mx31-regs.h, mx31.h instead of imx-regs.h and clock.h). This requires several nasty #ifdef in the drivers to include the correct header. The patch cleans up the driver and renames the header files as for the other i.MX processors. Signed-off-by: NStefano Babic <sbabic@denx.de>
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由 Fabio Estevam 提交于
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
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由 Stefano Babic 提交于
The patch add CONFIG_HW_WATCHDOG to be used with the internal watchdog timer of the MX31 processor. Two function are exported for the board maintainers: mxc_hw_watchdog_enable mxc_hw_watchdog_reset The board maintainer can decide to use mxc_hw_watchdog_reset as hw_watchdog_reset, or to implement his own function to reset the watchdog. The watchdog timer can be configured with CONFIG_SYS_WD_TIMER_SECS (value in seconds). The MX31 allows values between 0.5 (CONFIG_SYS_WD_TIMER_SECS = 0) and 128 seconds. Signed-off-by: NStefano Babic <sbabic@denx.de>
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- 13 4月, 2011 2 次提交
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由 Wolfgang Denk 提交于
Rename STANDALONE_LOAD_ADDR into CONFIG_STANDALONE_LOAD_ADDR and allow that the architecture-specific default value gets overwritten by defining the value in the board header file. Signed-off-by: NWolfgang Denk <wd@denx.de> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> Cc: Daniel Hellstrom <daniel@gaisler.com> Cc: Tsi Chung Liew <tsi-chung.liew@freescale.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Loïc Minier 提交于
Signed-off-by: NLoc Minier <loic.minier@linaro.org>
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- 28 3月, 2011 7 次提交
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由 Chander Kashyap 提交于
The MMC registers are accessed through struct s5p_mmc member variables. MMC controller "control4" register offset is set to 0x8C as per data sheet. The size of struct s5p_mmc is also corrected. Signed-off-by: NChander Kashyap <chander.kashyap@linaro.org> Signed-off-by: NTushar Behera <tushar.behera@linaro.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Minkyu Kang 提交于
Use the global data instead of bss variable, replace as follow. count_value -> removed timestamp -> tbl lastdec -> lastinc Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Acked-by: NAlbert ARIBAUD <albert.aribaud@free.fr>
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由 Minkyu Kang 提交于
Use pwm functions for timer that is PWM timer 4. Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Donghwa Lee 提交于
This is common pwm driver of S5P. Signed-off-by: NDonghwa Lee <dh09.lee@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 seedshope 提交于
Since nand boot have some limit for the first 4KB, We only disable the LED function to reduce the code space. At the same time, Fix the compile error for LED function undefined in the compile time of nand_spl. Signed-off-by: NZhong Hongbo <bocui107@gmail.com> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Po-Yu Chuang 提交于
Monitor protection region in FLASH did not cover .rel.dyn and .dynsym sections, because it uses __bss_start to compute monitor_flash_len. Use _end instead. Add _end to linker scripts for end of u-boot image Add _end_ofs to all the start.S. Signed-off-by: NPo-Yu Chuang <ratbert@faraday-tech.com>
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由 Po-Yu Chuang 提交于
Currently, _end is used for end of BSS section. We want _end to mean end of u-boot image, so we rename _end to __bss_end__ first. Signed-off-by: NPo-Yu Chuang <ratbert@faraday-tech.com>
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- 21 2月, 2011 7 次提交
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由 Sandeep Paulraj 提交于
This commit updates the mach-types based on the latest in linus's head Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>
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由 Fabio Estevam 提交于
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
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由 Fabio Estevam 提交于
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NMagnus Lilja <lilja.magnus@gmail.com> Tested-by: NMagnus Lilja <lilja.magnus@gmail.com>
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由 Po-Yu Chuang 提交于
get_sp() was incorrectly excluded if none of CONFIG_SETUP_MEMORY_TAGS CONFIG_CMDLINE_TAG CONFIG_INITRD_TAG CONFIG_SERIAL_TAG CONFIG_REVISION_TAG were defined. Signed-off-by: NPo-Yu Chuang <ratbert@faraday-tech.com>
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由 Lei Wen 提交于
This patch adds the Multiple Function Pin configuration support for Marvell PANTHEON SoCs Signed-off-by: NLei Wen <leiwen@marvell.com>
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由 Lei Wen 提交于
Pantheon Family processors are highly integrated SoCs based on Sheeva_88SV331x-v5 PJ1 cpu core. Ref: http://www.marvell.com/products/processors/communications/marvell_pantheon_910_920_pb.pdf SoC versions Supported: 1) PANTHEON920 (TD) 2) PANTHEON910 (TTC) Signed-off-by: NLei Wen <leiwen@marvell.com>
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由 Lei Wen 提交于
Since there are lots of difference between kirkwood and armada series, it is better to seperate them but still keep the most common file shared by all marvell platform in the mv-common configure file. This patch move the kirkwood only driver definitoin in mv-common to the <soc_name>/config.h. This patch is tested with compilation for armada100 and guruplug. Signed-off-by: NLei Wen <leiwen@marvell.com>
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