- 22 11月, 2015 1 次提交
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由 Thomas Chou 提交于
Move CONFIG_SYS_NS16550 to Kconfig, and run moveconfig.py. Signed-off-by: NThomas Chou <thomas@wytron.com.tw>
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- 22 8月, 2015 2 次提交
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由 Simon Glass 提交于
Move config for the E1000 Ethernet driver to Kconfig and tidy up affected boards. Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Simon Glass 提交于
Several files are out of order. This means that when the moveconfig tool moves CONFIG options to Kconfig it generates a large diff. To avoid this, reorder the files first. Signed-off-by: NSimon Glass <sjg@chromium.org>
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- 31 7月, 2015 2 次提交
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由 Aneesh Bansal 提交于
Secure Boot Target is added for NAND for P5020 and P5040. The Secure boot target has already been added for P3041 by enabling CONFIG_SYS_RAMBOOT and configuring CPC as SRAM. The targets for P5020 and P5040 are added in the same manner. Signed-off-by: NSaksham Jain <saksham@freescale.com> Signed-off-by: NRuchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Aneesh Bansal 提交于
Secure Boot Target is added for NAND for P3041. For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In case of secure boot, this default address maps to Boot ROM. The Boot ROM code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is configured as SRAM. U-Boot binary will be located on SRAM configured at address 0xBFF00000. In the U-Boot code, TLB entries are created to map the virtual address 0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM. Signed-off-by: NSaksham Jain <saksham@freescale.com> Signed-off-by: NRuchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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