Signed-off-by: NJana Rapava <fermata7@gmail.com>

On i.MX27, the asm-offsets.h file is not yet generated as it should be.
Signed-off-by: NStefano Babic <sbabic@denx.de>
CC: Matthias Weisser <weisserm@arcor.de>

On i.MX5, the asm-offsets.h file is not yet generated as it should be.
Signed-off-by: NStefano Babic <sbabic@denx.de>
CC: Matthias Weisser <weisserm@arcor.de>

zmx25 is a board based on imx25 SoC, 64 Megs of LPDDR, 32 Megs of NOR flash, an
optional NAND flash.
Signed-off-by: NMatthias Weisser <weisserm@arcor.de>

Adding support for mxc_gpio driver for imx25 and fix names of registers in tx25
board.
Signed-off-by: NMatthias Weisser <weisserm@arcor.de>

Offsets to registers may be needed in asm code. This patch adds automated
generation of these offsets form C structures.
Signed-off-by: NMatthias Weisser <weisserm@arcor.de>

Adding support for USB host on imx25 using the internal PHY. Changing the name
of base address define for imx31 to get some unification.
Signed-off-by: NMatthias Weisser <weisserm@arcor.de>

imx25 used the wrong reset.c from imx27
Signed-off-by: NMatthias Weisser <weisserm@arcor.de>

Need this function for autoboot keyd
Signed-off-by: NMatthias Weisser <weisserm@arcor.de>

Signed-off-by: NTorsten Koschorrek <koschorrek@synertronixx.de>

mx27_uart_init_pins does the IOMUX setting for UART1 port.

Change the function name to make the UART port number explicit.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

asm-offsets.h should be auto generated. This patch adds two rules to rules.mk
which makes this possible and removes the rules on imx35.
Signed-off-by: NMatthias Weisser <weisserm@arcor.de>
Acked-by: NStefano Babic <sbabic@denx.de>

Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

Move to use hwconfig for usb mode & phy type instead of magic
'usb_phy_type' environment variable on the following platforms:

MPC8536DS, P1020RDB, P1020RDB-PC, P1010RDB, P2020RDB, P2020RDB-PC,
P2020RDB, P3041DS, P4080DS, & P5020DS.
Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Enable buffer write for better performance. This platform uses a NOR flash
chip which supports write buffer programming. CFI driver can query the
buffer size and use it to program the flash for best performance.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Some P4080 rev1 errata work-arounds, notably erratum SERDES4, required a
bank soft-reset after the bank was configured and enabled, even though
enabling a bank causes it to reset.  Because the reset was required for
multiple errata, it was not properly enclosed in an #ifdef, and so was
not removed with all the other rev1 errata work-arounds.

Erratum SERDES-8 says that the clocks for bank 3 needs to be enabled if
bank 2 is enabled, but this was not being done for SERDES protocols 0xF
and 0x10.  The bank reset also happened to enable bank 3 (apparently an
undocumented feature).  Simply removing the reset breaks these two
protocols.

It turns out that every time we call enable_bank(), we do want at least
one lane of the bank enabled, either because the bank is supposed to be
enabled, or because we need the clock from that bank enabled.

For erratum SERDES-A001, we don't want to modify srds_lpd_b[] when we
call enable_bank(), because that array is used elsewhere to determine if
the bank is available.

Note that the side effect of these changes is that the work-arounds for
these two errata are now linked.  Specifically, if SERDES-A001 is
enabled, then we need SERDES-8 enabled as well.

Because this was the only SERDES bank soft-reset, there is no need to
implement a work-around for erratum SERDES-A003.

Also fix an off-by-one error in a printf().
Signed-off-by: NTimur Tabi <timur@freescale.com>
Acked-by: NEd Swarthout <swarthou@freescale.com>
Acked-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add this option to allow boards to override the default read-to-write
turnaround time for better performance.
Signed-off-by: NYork Sun <yorksun@freescale.com>

Resolve P1020 second USB controller multiplexing with eLBC
	- mandatory to mention USB2 in hwconfig string to select it
	  over eLBC, otherwise USB2 node is removed
	- works only for SPI and SD boot
Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Specify hwconfig usage for USB mode and phy change
Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Modify support for USB mode fixup:
        - Add common support for USB mode and phy type
          device tree fix-up for all USB controllers
          mentioned in hwconfig string
        - Fetch USB mode and phy type via hwconfig; if not
          defined in hwconfig, then fetch them from env
Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The P1023RDS board is the reference board for the P1023 SoC.

Add support for booting it from NOR or NAND, with fixed 2G of DDR, PCIe,
UART, I2C, etc.
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: NChunhe Lan <Chunhe.Lan@freescale.com>
Signed-off-by: NLei Xu <B33228@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

If DDR initialziation uses a speed table and the speed is not matched,
print a warning message instead of silently ignoring.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Allow overriding RCW for all RDIMM, not only quad-rank ones.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Checking width before setting DDR controller. SPD for DDR1 and DDR2 has
data width and primary sdram width. The latter one has different meaning
for DDR3.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

In case of empty SPD or checksum error, fallback to raw timing on
supported boards.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

We used to have fixed parameters for soldered DDR chips. This patch
introduces CONFIG_SYS_DDR_RAW_TIMING to enable calculation based on timing
data from DDR chip datasheet, implemneted in board-specific files or header
files.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

On P1022/P1013 second USB controller is muxed with second
Ethernet controller. The current code to enable second USB
fails to properly clear pinmux bits used by ethernet. As a
result, Linux freezes when this controller is used. This
patch fixes the problem.
Signed-off-by: NFelix Radensky <felix@embedded-sol.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Adding byte 32 and 33
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add support for 16-bit DDR bus. Also deal with system using 64- and 32-bit
DDR devices.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Only use DDR DIMM part number if SPD has valid length, to prevent from
display garbage in case SPD doesn't cover these fields.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

If the bus width is 32-bit, burst chop should be disabled and burst length
should be 8. Read from SPD or other source to determine the width.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

When booting from NAND we get the environment and FMan ucode from NAND.
Signed-off-by: NShaohui Xie <b21989@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The P2041 is similar to P2040, however has a 10G port and backside L2
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add P2040 SoC specific information:
* LIODN setup
* Portal configuration
* etc
Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add ifdef protection for qp_info and liodn associated with Q/BMan.  Also
rearrange setting of _tbl_sz variables to utilize existing ifdef
protection for things like FMAN.

Also add protection around setup_portals() call in corenet_ds board
code.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add CONFIG_HAS_FSL_DR_USB macro for P1020RDB
Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add ifdef protection in LBC code to handle the case in which
CONFIG_SYS_BR0_PRELIM and CONFIG_SYS_OR0_PRELIM arent defined for a
build.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add ifdef protection in LAW & TLB code to handle the case in which
CONFIG_SYS_BMAN_MEM_PHYS or CONFIG_SYS_QMAN_MEM_PHYS arent defined for a
build.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

On a 8308 based board it was found that the PEX_GLK_RATIO register
(programmed in arch/powerpc/cpu/mpc83xx/pcie.c) was getting set to 0, This
was tracked to the fact that the pci express clock frequency was not being
assigned to the pciexp1_clk entry in the global data structure in file
arch/powerpc/cpu/mpc83xx/speed.c. Fix this and a similiar issue in
'do_clocks' command.
Signed-off-by: NBill Cook <cook@isgchips.com>
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>